GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/zork: Apply USB2 default phy tune parameter for Zork family 

Apply the default USB2 phy tuning parameter for Zork family

BUG=b:155132211
TEST=Build, verified the default value been applied on trembyle
and the USB2 device works well.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I1f00b04173796d70147e232bafa405487b0761e1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2260216
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42997
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Chris Wang 2020-06-23 21:10:57 +08:00 committed by Patrick Georgi
parent 04dfc26f94
commit 1e3e528d23
1 changed files with 78 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

78
src/mainboard/google/zork/variants/baseboard/devicetree.cb
View File

@ -60,6 +60,84 @@ chip soc/amd/picasso
register "xhci0_force_gen1" = "0"
# Controller0 Port0 Default
register "usb_2_port_0_tune_params" = "{
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
# Controller0 Port1 Default
register "usb_2_port_1_tune_params" = "{
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
# Controller0 Port2 Default
register "usb_2_port_2_tune_params" = "{
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
# Controller0 Port3 Default
register "usb_2_port_3_tune_params" = "{
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
# Controller1 Port0 Default
register "usb_2_port_4_tune_params" = "{
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x02,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x5,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
# Controller1 Port1 Default
register "usb_2_port_5_tune_params" = "{
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x02,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x5,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
# SPI Configuration
register "common_config.spi_config" = "{
.normal_speed = SPI_SPEED_66M, /* MHz */