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soc/intel: Enable TME based on supported CPU SKU and config option 

This patch removes the static kconfig being used to fill in TME enable
FSP UPD. Instead use`is_tme_supported()` and `CONFIG(INTEL_TME)` to check
if the CPU has required TME support rather than hardcoding.

TEST=FSP debug log shows `TmeEnable` UPD is set appropriately for the
TME-supported CPU SKUs.

As per FSP-M debug log:

Without this CL, Alder Lake-P CPU SKU without TME support:
[SPEW ]   TmeEnable = 0x1

With this CL, Alder Lake-P CPU SKU without TME support:
[SPEW ]   TmeEnable = 0x0

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8aa2922baaf2a49e6e2762d31eaffa7bdcd43b0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66750
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2022-08-15 15:40:59 +05:30 committed by Martin L Roth
parent 28f1729f15
commit 1e71fe107a
3 changed files with 3 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/alderlake/romstage/fsp_params.c
View File

@ -177,7 +177,7 @@ static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg,
{ {
/* Disable BIOS Guard */ /* Disable BIOS Guard */
m_cfg->BiosGuard = 0; m_cfg->BiosGuard = 0;
m_cfg->TmeEnable = CONFIG(INTEL_TME); m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported();
} }
static void fill_fspm_uart_params(FSP_M_CONFIG *m_cfg, static void fill_fspm_uart_params(FSP_M_CONFIG *m_cfg,

2
src/soc/intel/meteorlake/romstage/fsp_params.c
View File

@ -134,7 +134,7 @@ static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg,
{ {
/* Disable BIOS Guard */ /* Disable BIOS Guard */
m_cfg->BiosGuard = 0; m_cfg->BiosGuard = 0;
m_cfg->TmeEnable = CONFIG(INTEL_TME); m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported();
} }
static void fill_fspm_uart_params(FSP_M_CONFIG *m_cfg, static void fill_fspm_uart_params(FSP_M_CONFIG *m_cfg,

3
src/soc/intel/tigerlake/romstage/fsp_params.c
View File

@ -206,8 +206,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->CpuPcieRpEnableMask |= 1 << i; m_cfg->CpuPcieRpEnableMask |= 1 << i;
} }
/* Change TmeEnable UPD value according to INTEL_TME Kconfig */ m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported();
m_cfg->TmeEnable = CONFIG(INTEL_TME);
/* crashLog config */ /* crashLog config */
m_cfg->CpuCrashLogDevice = CONFIG(SOC_INTEL_CRASHLOG) && is_devfn_enabled(SA_DEVFN_TMT); m_cfg->CpuCrashLogDevice = CONFIG(SOC_INTEL_CRASHLOG) && is_devfn_enabled(SA_DEVFN_TMT);