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coreboot-kgpe-d16
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Drop romcc related stuff, as this board only uses CAR. 

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2684 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2007-05-21 21:33:24 +00:00
parent 931d922176
commit 1e79f12654
3 changed files with 8 additions and 31 deletions
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26
src/mainboard/amd/norwich/Config.lb
View File

@ -49,8 +49,8 @@ driver mainboard.o
if HAVE_PIRQ_TABLE
object irq_tables.o
end
#object reset.o
#object reset.o
if USE_DCACHE_RAM
#compile cache_as_ram.c to auto.inc
@ -63,29 +63,6 @@ if USE_DCACHE_RAM
end
##
## Romcc output
##
#makerule ./failover.E
# depends "$(MAINBOARD)/failover.c ./romcc"
# action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
#end
#
#makerule ./failover.inc
# depends "$(MAINBOARD)/failover.c ./romcc"
# action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
#end
#
#makerule ./auto.E
# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
# action "./romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
#end
#makerule ./auto.inc
# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
# action "./romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
#end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
@ -183,6 +160,5 @@ chip northbridge/amd/lx
device apic 0 on end
end
end
end

12
src/mainboard/amd/norwich/cache_as_ram_auto.c
View File

@ -24,7 +24,6 @@
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
@ -109,11 +108,14 @@ void cache_as_ram_main(void)
cs5536_early_setup();
/* Note: must do this AFTER the early_setup! It is counting on some early
* MSR setup for CS5536.
/* Note: must do this AFTER the early_setup! It is counting on some
* early MSR setup for CS5536.
*/
/* cs5536_disable_internal_uart disable them for now, set them up later... */
cs5536_setup_onchipuart(); /* if debug. real setup done in chipset init via config.lb */
/* cs5536_disable_internal_uart: disable them for now, set them
* up later...
*/
/* If debug. real setup done in chipset init via Config.lb. */
cs5536_setup_onchipuart();
mb_gpio_init();
uart_init();
console_init();

1
src/mainboard/amd/norwich/failover.c
View File

@ -3,7 +3,6 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include "arch/romcc_io.h"
#include "pc80/mc146818rtc_early.c"
static unsigned long main(unsigned long bist)