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soc/intel/jasperlake: add pcie modphy settings 

This patch adds device tree settings to control pcie modphy tuning
FSP UPDs. With this patch, the pcie modphy can be tuned per board.

BUG=b:192716633
BRANCH=NONE
TEST=build dedede variant coreboot with fw_debug enable and check if
     these settings have been changed successfully on fsp debug log.

Change-Id: I80a91d45f9dd8ef218846e1284fdad309313e831
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Jamie Chen 2021-07-20 18:33:57 +08:00 committed by Patrick Georgi
parent 0f93a7b781
commit 1ebcb2ab62
3 changed files with 62 additions and 0 deletions
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4
src/soc/intel/jasperlake/chip.h
View File

@ -13,6 +13,7 @@
#include <soc/gpio.h>
#include <soc/pch.h>
#include <soc/pci_devs.h>
#include <soc/pcie_modphy.h>
#include <soc/pmc.h>
#include <soc/serialio.h>
#include <soc/usb.h>
@ -122,6 +123,9 @@ struct soc_intel_jasperlake_config {
/* PCIe RP L1 substate */
enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
/* PCIe ModPhy related */
struct pcie_modphy_config pcie_mp_cfg[CONFIG_MAX_ROOT_PORTS];
/* SMBus */
uint8_t SmbusEnable;

24
src/soc/intel/jasperlake/include/soc/pcie_modphy.h Normal file
View File

@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _SOC_JASPERLAKE_PCIE_MODPHY_H_
#define _SOC_JASPERLAKE_PCIE_MODPHY_H_
struct pcie_modphy_config {
/* TX Output Downscale Amplitude Adjustment */
bool tx_gen1_downscale_amp_override;
uint8_t tx_gen1_downscale_amp;
/* TX Output Downscale Amplitude Adjustment */
bool tx_gen2_downscale_amp_override;
uint8_t tx_gen2_downscale_amp;
/* TX Output Downscale Amplitude Adjustment */
bool tx_gen3_downscale_amp_override;
uint8_t tx_gen3_downscale_amp;
/* TX Output -3.5dB Mode De-Emphasis Adjustment Setting */
uint8_t tx_gen1_de_emph;
/* TX Output -3.5dB Mode De-Emphasis Adjustment Setting */
uint8_t tx_gen2_de_emph_3p5;
/* TX Output -6.0dB Mode De-Emphasis Adjustment Setting */
uint8_t tx_gen2_de_emph_6p0;
};
#endif

34
src/soc/intel/jasperlake/romstage/fsp_params.c
View File

@ -27,6 +27,40 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->SaGv = config->SaGv;
m_cfg->RMT = config->RMT;
/* PCIe ModPhy configuration */
for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
if (config->pcie_mp_cfg[i].tx_gen1_downscale_amp_override) {
m_cfg->PchPcieHsioTxGen1DownscaleAmpEnable[i] = 1;
m_cfg->PchPcieHsioTxGen1DownscaleAmp[i] =
config->pcie_mp_cfg[i].tx_gen1_downscale_amp;
}
if (config->pcie_mp_cfg[i].tx_gen2_downscale_amp_override) {
m_cfg->PchPcieHsioTxGen2DownscaleAmpEnable[i] = 1;
m_cfg->PchPcieHsioTxGen2DownscaleAmp[i] =
config->pcie_mp_cfg[i].tx_gen2_downscale_amp;
}
if (config->pcie_mp_cfg[i].tx_gen3_downscale_amp_override) {
m_cfg->PchPcieHsioTxGen3DownscaleAmpEnable[i] = 1;
m_cfg->PchPcieHsioTxGen3DownscaleAmp[i] =
config->pcie_mp_cfg[i].tx_gen3_downscale_amp;
}
if (config->pcie_mp_cfg[i].tx_gen1_de_emph) {
m_cfg->PchPcieHsioTxGen1DeEmphEnable[i] = 1;
m_cfg->PchPcieHsioTxGen1DeEmph[i] =
config->pcie_mp_cfg[i].tx_gen1_de_emph;
}
if (config->pcie_mp_cfg[i].tx_gen2_de_emph_3p5) {
m_cfg->PchPcieHsioTxGen2DeEmph3p5Enable[i] = 1;
m_cfg->PchPcieHsioTxGen2DeEmph3p5[i] =
config->pcie_mp_cfg[i].tx_gen2_de_emph_3p5;
}
if (config->pcie_mp_cfg[i].tx_gen2_de_emph_6p0) {
m_cfg->PchPcieHsioTxGen2DeEmph6p0Enable[i] = 1;
m_cfg->PchPcieHsioTxGen2DeEmph6p0[i] =
config->pcie_mp_cfg[i].tx_gen2_de_emph_6p0;
}
}
/* PCIe root port configuration */
for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
if (config->PcieRpEnable[i])