diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index c79eb08c7b..a73657ee2c 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -317,6 +317,12 @@ config SOC_INTEL_ALDERLAKE_S3
 	help
 	  Select if using S3 instead of S0ix to disable D3Cold.
 
+config ENABLE_SATA_TEST_MODE
+	bool "Enable test mode for SATA margining"
+	default n
+	help
+	  Enable SATA test mode in FSP-S.
+
 config SOC_INTEL_UART_DEV_MAX
 	int
 	default 7
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 016d8ad3ab..5346403705 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -757,6 +757,8 @@ static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg,
 	 * these disable variables to 1 in devicetree overrides.
 	 */
 	s_cfg->SataPwrOptEnable = !(config->sata_pwr_optimize_disable);
+	/* Test mode for SATA margining */
+	s_cfg->SataTestMode = CONFIG(ENABLE_SATA_TEST_MODE);
 	/*
 	 *  Enable DEVSLP Idle Timeout settings DmVal and DitoVal.
 	 *  SataPortsDmVal is the DITO multiplier. Default is 15.