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tegra124: Fix PWM pinmux functions 

It seems that someone just stuck the PM3 function for all of the potential
PWM pins.  Fix this to be more specific to the particular PWM (of which
there are four).

BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan

Original-Change-Id: Ic61a7321fbe28953b22007a1d0b522c3ca8714ad
Original-Signed-off-by: Andrew Chew <achew@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/185739
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
(cherry picked from commit f19f897fe11a582cc240d98de88c5e2d4dc4e364)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ie10173413a5f00e06f5b1803fd93d6cb322cee3d
Reviewed-on: http://review.coreboot.org/7399
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Andrew Chew 2014-02-10 16:31:23 -08:00 committed by Marc Jones
parent 33ddd1f2ff
commit 1ecbc8cf56
1 changed files with 16 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
src/soc/nvidia/tegra124/pinmux.h
View File

@ -53,8 +53,8 @@ enum {
PINMUX_CONSTANTS(18, SDMMC1_CLK, Z0, SDMMC1, CLK12M, RES2, RES3),
PINMUX_CONSTANTS(19, SDMMC1_CMD, Z1, SDMMC1, SPDIF, SPI4, UA3),
PINMUX_CONSTANTS(20, SDMMC1_DAT3, Y4, SDMMC1, SPDIF, SPI4, UA3),
PINMUX_CONSTANTS(21, SDMMC1_DAT2, Y5, SDMMC1, PM3, SPI4, UA3),
PINMUX_CONSTANTS(22, SDMMC1_DAT1, Y6, SDMMC1, PM3, SPI4, UA3),
PINMUX_CONSTANTS(21, SDMMC1_DAT2, Y5, SDMMC1, PWM0, SPI4, UA3),
PINMUX_CONSTANTS(22, SDMMC1_DAT1, Y6, SDMMC1, PWM1, SPI4, UA3),
PINMUX_CONSTANTS(23, SDMMC1_DAT0, Y7, SDMMC1, RES1, SPI4, UA3),
PINMUX_CONSTANTS(26, CLK2_OUT, W5, EXTPERIPH2, RES1, RES2, RES3),
PINMUX_CONSTANTS(27, CLK2_REQ, CC5, DAP, RES1, RES2, RES3),
@ -68,14 +68,14 @@ enum {
PINMUX_CONSTANTS(93, UART3_TXD, W6, UC3, RES1, NOR, SPI4),
PINMUX_CONSTANTS(94, UART3_RXD, W7, UC3, RES1, NOR, SPI4),
PINMUX_CONSTANTS(95, UART3_CTS_N, A1, UC3, SDMMC1, DTV, NOR),
PINMUX_CONSTANTS(96, UART3_RTS_N, C0, UC3, PM3, DTV, NOR),
PINMUX_CONSTANTS(96, UART3_RTS_N, C0, UC3, PWM0, DTV, NOR),
PINMUX_CONSTANTS(97, GPIO_PU0, U0, OWR, UA3, NOR, RES3),
PINMUX_CONSTANTS(98, GPIO_PU1, U1, RES0, UA3, NOR, RES3),
PINMUX_CONSTANTS(99, GPIO_PU2, U2, RES0, UA3, NOR, RES3),
PINMUX_CONSTANTS(100, GPIO_PU3, U3, PM3, UA3, NOR, DCB),
PINMUX_CONSTANTS(101, GPIO_PU4, U4, PM3, UA3, NOR, DCB),
PINMUX_CONSTANTS(102, GPIO_PU5, U5, PM3, UA3, NOR, DCB),
PINMUX_CONSTANTS(103, GPIO_PU6, U6, PM3, UA3, RES2, NOR),
PINMUX_CONSTANTS(100, GPIO_PU3, U3, PWM0, UA3, NOR, DCB),
PINMUX_CONSTANTS(101, GPIO_PU4, U4, PWM1, UA3, NOR, DCB),
PINMUX_CONSTANTS(102, GPIO_PU5, U5, PWM2, UA3, NOR, DCB),
PINMUX_CONSTANTS(103, GPIO_PU6, U6, PWM3, UA3, RES2, NOR),
PINMUX_CONSTANTS(104, GEN1_I2C_SDA, C5, I2C1, RES1, RES2, RES3),
PINMUX_CONSTANTS(105, GEN1_I2C_SCL, C4, I2C1, RES1, RES2, RES3),
PINMUX_CONSTANTS(106, DAP4_FS, P4, I2S3, NOR, DTV, RES3),
@ -104,10 +104,10 @@ enum {
PINMUX_CONSTANTS(129, GPIO_PG5, G5, RES0, RES1, NOR, SPI4),
PINMUX_CONSTANTS(130, GPIO_PG6, G6, RES0, RES1, NOR, SPI4),
PINMUX_CONSTANTS(131, GPIO_PG7, G7, RES0, RES1, NOR, SPI4),
PINMUX_CONSTANTS(132, GPIO_PH0, H0, PM3, TRACE, NOR, DTV),
PINMUX_CONSTANTS(133, GPIO_PH1, H1, PM3, TMDS, NOR, DCA),
PINMUX_CONSTANTS(134, GPIO_PH2, H2, PM3, TDMS, NOR, CLDVFS),
PINMUX_CONSTANTS(135, GPIO_PH3, H3, PM3, SPI4, NOR, CLDVFS),
PINMUX_CONSTANTS(132, GPIO_PH0, H0, PWM0, TRACE, NOR, DTV),
PINMUX_CONSTANTS(133, GPIO_PH1, H1, PWM1, TMDS, NOR, DCA),
PINMUX_CONSTANTS(134, GPIO_PH2, H2, PWM2, TDMS, NOR, CLDVFS),
PINMUX_CONSTANTS(135, GPIO_PH3, H3, PWM3, SPI4, NOR, CLDVFS),
PINMUX_CONSTANTS(136, GPIO_PH4, H4, SDMMC2, RES1, NOR, RES3),
PINMUX_CONSTANTS(137, GPIO_PH5, H5, SDMMC2, RES1, NOR, RES3),
PINMUX_CONSTANTS(138, GPIO_PH6, H6, SDMMC2, TRACE, NOR, DTV),
@ -167,7 +167,7 @@ enum {
PINMUX_CONSTANTS(191, KB_COL0, Q0, RES0, RES1, SPI2, RES3),
PINMUX_CONSTANTS(192, KB_COL1, Q1, RES0, RES1, SPI2, RES3),
PINMUX_CONSTANTS(193, KB_COL2, Q2, RES0, RES1, SPI2, RES3),
PINMUX_CONSTANTS(194, KB_COL3, Q3, RES0, DCA, PM3, UA3),
PINMUX_CONSTANTS(194, KB_COL3, Q3, RES0, DCA, PWM2, UA3),
PINMUX_CONSTANTS(195, KB_COL4, Q4, RES0, OWR, SDMMC3, UA3),
PINMUX_CONSTANTS(196, KB_COL5, Q5, RES0, RES1, SDMMC3, RES3),
PINMUX_CONSTANTS(197, KB_COL6, Q6, RES0, RES1, SPI2, UD3),
@ -200,11 +200,11 @@ enum {
PINMUX_CONSTANTS(224, GPIO_X6_AUD, X6, SPI6, SPI1, SPI2, NOR),
PINMUX_CONSTANTS(225, GPIO_X7_AUD, X7, RES0, SPI1, SPI2, RES3),
PINMUX_CONSTANTS(228, SDMMC3_CLK, A6, SDMMC3, RES1, RES2, SPI3),
PINMUX_CONSTANTS(229, SDMMC3_CMD, A7, SDMMC3, PM3, UA3, SPI3),
PINMUX_CONSTANTS(229, SDMMC3_CMD, A7, SDMMC3, PWM3, UA3, SPI3),
PINMUX_CONSTANTS(230, SDMMC3_DAT0, B7, SDMMC3, RES1, RES2, SPI3),
PINMUX_CONSTANTS(231, SDMMC3_DAT1, B6, SDMMC3, PM3, UA3, SPI3),
PINMUX_CONSTANTS(232, SDMMC3_DAT2, B5, SDMMC3, PM3, DCA, SPI3),
PINMUX_CONSTANTS(233, SDMMC3_DAT3, B4, SDMMC3, PM3, DCB, SPI3),
PINMUX_CONSTANTS(231, SDMMC3_DAT1, B6, SDMMC3, PWM2, UA3, SPI3),
PINMUX_CONSTANTS(232, SDMMC3_DAT2, B5, SDMMC3, PWM1, DCA, SPI3),
PINMUX_CONSTANTS(233, SDMMC3_DAT3, B4, SDMMC3, PWM0, DCB, SPI3),
PINMUX_CONSTANTS(239, PEX_L0_RST_N, DD1, PE0, RES1, RES2, RES3),
PINMUX_CONSTANTS(240, PEX_L0_CLKREQ_N, DD2, PE0, RES1, RES2, RES3),
PINMUX_CONSTANTS(241, PEX_WAKE_N, DD3, PE, RES1, RES2, RES3),