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mainboard/intel: Update mainboard UART Kconfig 

After a96e66a (soc/intel: Clean mess around UART_DEBUG) got merged,
all mainboard using intel cannonlake,coffeelake, kabylake, skylake,
icelake and whiskeylake get affected.

Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG
and set default console for each platform.

TEST=Intel client and IoT team has verified that LPSS uart
is working fine on CNL, WHL and ICL RVPs.

Change-Id: I0381a6616f03c74c98f837e3c008459fefd4818c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30913
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2019-01-14 20:03:56 +05:30 committed by Patrick Georgi
parent d4a12ec822
commit 1ed36f9ce9
4 changed files with 17 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/mainboard/intel/cannonlake_rvp/Kconfig
View File

@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS
select DRIVERS_I2C_GENERIC select DRIVERS_I2C_GENERIC
select SOC_INTEL_CANNONLAKE select SOC_INTEL_CANNONLAKE
select MAINBOARD_USES_IFD_EC_REGION select MAINBOARD_USES_IFD_EC_REGION
select INTEL_LPSS_UART_FOR_CONSOLE
config MAINBOARD_DIR config MAINBOARD_DIR
string string
@ -65,4 +66,8 @@ config DIMM_SPD_SIZE
config VBOOT config VBOOT
select VBOOT_LID_SWITCH select VBOOT_LID_SWITCH
select VBOOT_MOCK_SECDATA select VBOOT_MOCK_SECDATA
config UART_FOR_CONSOLE
int
default 2
endif endif

5
src/mainboard/intel/coffeelake_rvp/Kconfig
View File

@ -7,7 +7,7 @@ config BOARD_SPECIFIC_OPTIONS
select GENERIC_SPD_BIN select GENERIC_SPD_BIN
select HAVE_ACPI_RESUME select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES
select INTEL_LPSS_UART_FOR_CONSOLE if BOARD_INTEL_WHISKEYLAKE_RVP select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS
select GENERIC_SPD_BIN select GENERIC_SPD_BIN
select DRIVERS_I2C_HID select DRIVERS_I2C_HID
@ -51,8 +51,7 @@ config MAX_CPUS
config UART_FOR_CONSOLE config UART_FOR_CONSOLE
int int
default 2 if BOARD_INTEL_WHISKEYLAKE_RVP default 2
default 0
config DEVICETREE config DEVICETREE
string string

5
src/mainboard/intel/icelake_rvp/Kconfig
View File

@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SOC_INTEL_ICELAKE select SOC_INTEL_ICELAKE
select MAINBOARD_USES_IFD_EC_REGION select MAINBOARD_USES_IFD_EC_REGION
select INTEL_LPSS_UART_FOR_CONSOLE
config MAINBOARD_DIR config MAINBOARD_DIR
string string
@ -51,4 +52,8 @@ config DIMM_SPD_SIZE
config VBOOT config VBOOT
select VBOOT_LID_SWITCH select VBOOT_LID_SWITCH
select VBOOT_MOCK_SECDATA select VBOOT_MOCK_SECDATA
config UART_FOR_CONSOLE
int
default 2
endif endif

5
src/mainboard/intel/kblrvp/Kconfig
View File

@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS
select GENERIC_SPD_BIN select GENERIC_SPD_BIN
select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_LPC_TPM
select INTEL_LPSS_UART_FOR_CONSOLE
config VBOOT config VBOOT
select VBOOT_LID_SWITCH select VBOOT_LID_SWITCH
@ -84,4 +85,8 @@ config PRERAM_CBMEM_CONSOLE_SIZE
config DIMM_SPD_SIZE config DIMM_SPD_SIZE
int int
default 512 if BOARD_INTEL_KBLRVP8 || BOARD_INTEL_KBLRVP11 #DDR4 default 512 if BOARD_INTEL_KBLRVP8 || BOARD_INTEL_KBLRVP11 #DDR4
config UART_FOR_CONSOLE
int
default 2
endif endif