From 1ed5a63c8c8b2680ee4371427aa6482a59777326 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 4 May 2021 21:51:43 +0200 Subject: [PATCH] soc/amd/cezanne: add GNB IOAPIC support To configure and enable the IOAPIC in the graphics and northbridge (GNB) container, FSP needs to write an undocumented register, so pass the GNB IOAPIC MMIO base address to make it show up at that address. BUG=b:187083211 TEST=Boot guybrush and see IO-APIC initialized IOAPIC[0]: apic_id 16, version 33, address 0xfec00000, GSI 0-23 IOAPIC[1]: apic_id 17, version 33, address 0xfec01000, GSI 24-55 Signed-off-by: Felix Held Signed-off-by: Raul E Rangel Change-Id: I1e127ce500d052783f0a6e13fb2ad16a8e408b0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52905 Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/acpi.c | 3 ++- src/soc/amd/cezanne/fsp_m_params.c | 9 +++++++++ src/soc/amd/cezanne/include/soc/iomap.h | 2 ++ src/soc/amd/cezanne/root_complex.c | 16 ++++++++++++++++ 4 files changed, 29 insertions(+), 1 deletion(-) diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index fd11589c66..180a1e5062 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -28,7 +28,8 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, FCH_IOAPIC_ID, IO_APIC_ADDR, 0); - /* TODO: Add GNB-IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, + GNB_IOAPIC_ID, GNB_IO_APIC_ADDR, IO_APIC_INTERRUPTS); current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *)current, diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 8da38ffa14..4aff7e09bb 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -50,6 +51,13 @@ static void fsp_fill_pcie_ddi_descriptors(FSP_M_CONFIG *mcfg) fill_ddi_descriptors(mcfg, fsp_ddi, num_ddi); } +static void fsp_assign_ioapic_upds(FSP_M_CONFIG *mcfg) +{ + mcfg->gnb_ioapic_base = GNB_IO_APIC_ADDR; + mcfg->gnb_ioapic_id = GNB_IOAPIC_ID; + mcfg->fch_ioapic_id = FCH_IOAPIC_ID; +} + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSP_M_CONFIG *mcfg = &mupd->FspmConfig; @@ -129,4 +137,5 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) config->telemetry_vddcrsocoffset; fsp_fill_pcie_ddi_descriptors(mcfg); + fsp_assign_ioapic_upds(mcfg); } diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index 83bb8176fa..486e3cf961 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -11,6 +11,8 @@ #if ENV_X86 /* MMIO Ranges */ +/* IO_APIC_ADDR defined in arch/x86 0xfec00000 */ +#define GNB_IO_APIC_ADDR 0xfec01000 #define SPI_BASE_ADDRESS 0xfec10000 #if CONFIG(HPET_ADDRESS_OVERRIDE) diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index ba846810c8..5d021baa5b 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include +#include #include #include #include @@ -9,6 +11,7 @@ #include #include #include +#include #include /* @@ -70,6 +73,7 @@ static void read_resources(struct device *dev) unsigned int idx = 0; const struct hob_header *hob = fsp_get_hob_list(); const struct hob_resource *res; + struct resource *gnb_apic; uintptr_t early_reserved_dram_start, early_reserved_dram_end; const struct memmap_early_dram *e = memmap_get_early_dram_usage(); @@ -129,6 +133,17 @@ static void read_resources(struct device *dev) printk(BIOS_ERR, "Error: failed to set resources for type %d\n", res->type); } + + /* GNB IOAPIC resource */ + gnb_apic = new_resource(dev, GNB_IO_APIC_ADDR); + gnb_apic->base = GNB_IO_APIC_ADDR; + gnb_apic->size = 0x00001000; + gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void root_complex_init(struct device *dev) +{ + setup_ioapic((u8 *)GNB_IO_APIC_ADDR, GNB_IOAPIC_ID); } static void root_complex_fill_ssdt(const struct device *device) @@ -145,6 +160,7 @@ static struct device_operations root_complex_operations = { .read_resources = read_resources, .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, + .init = root_complex_init, .acpi_name = gnb_acpi_name, .acpi_fill_ssdt = root_complex_fill_ssdt, };