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nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetree 

Change-Id: I0a7b3167392c152da6459dfc202ef11b2e61400a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69295
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2022-11-07 10:04:56 +01:00
parent 22d6ee8d9c
commit 1eecb8c814
19 changed files with 74 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/acer/g43t-am3/devicetree.cb
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@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/x4x # Northbridge
device cpu_cluster 0 on # APIC cluster
device cpu_cluster 0 on
ops x4x_cpu_bus_ops # APIC cluster
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge
device lapic 0xacac off end
end
end
device domain 0 on # PCI domain
device domain 0 on
ops x4x_pci_domain_ops # PCI domain
subsystemid 0x8086 0x0028 inherit
device pci 0.0 on end # Host Bridge
device pci 2.0 on end # Integrated graphics controller

6
src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb
View File

@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/x4x # Northbridge
device cpu_cluster 0 on # APIC cluster
device cpu_cluster 0 on
ops x4x_cpu_bus_ops # APIC cluster
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge
device lapic 0xACAC off end
end
end
device domain 0 on # PCI domain
device domain 0 on
ops x4x_pci_domain_ops # PCI domain
subsystemid 0x1458 0x5000 inherit
device pci 0.0 on # Host Bridge
subsystemid 0x1849 0x2e30

6
src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb
View File

@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/x4x # Northbridge
device cpu_cluster 0 on # APIC cluster
device cpu_cluster 0 on
ops x4x_cpu_bus_ops # APIC cluster
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge
device lapic 0xACAC off end
end
end
device domain 0 on # PCI domain
device domain 0 on
ops x4x_pci_domain_ops # PCI domain
subsystemid 0x1458 0x5000 inherit
device pci 0.0 on # Host Bridge
subsystemid 0x1849 0x2e30

6
src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb
View File

@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/x4x # Northbridge
device cpu_cluster 0 on # APIC cluster
device cpu_cluster 0 on
ops x4x_cpu_bus_ops # APIC cluster
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge
device lapic 0xACAC off end
end
end
device domain 0 on # PCI domain
device domain 0 on
ops x4x_pci_domain_ops # PCI domain
subsystemid 0x1458 0x5000 inherit
device pci 0.0 on # Host Bridge
subsystemid 0x1849 0x2e30

6
src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb
View File

@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/x4x # Northbridge
device cpu_cluster 0 on # APIC cluster
device cpu_cluster 0 on
ops x4x_cpu_bus_ops # APIC cluster
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge
device lapic 0xACAC off end
end
end
device domain 0 on # PCI domain
device domain 0 on
ops x4x_pci_domain_ops # PCI domain
subsystemid 0x1458 0x5000 inherit
device pci 0.0 on # Host Bridge
subsystemid 0x1849 0x2e30

6
src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb
View File

@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/x4x # Northbridge
device cpu_cluster 0 on # APIC cluster
device cpu_cluster 0 on
ops x4x_cpu_bus_ops # APIC cluster
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge
device lapic 0xACAC off end
end
end
device domain 0 on # PCI domain
device domain 0 on
ops x4x_pci_domain_ops # PCI domain
subsystemid 0x1458 0x5000 inherit
device pci 0.0 on # Host Bridge
subsystemid 0x1849 0x2e30

6
src/mainboard/asus/p5qc/variants/p5q/devicetree.cb
View File

@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/x4x # Northbridge
device cpu_cluster 0 on # APIC cluster
device cpu_cluster 0 on
ops x4x_cpu_bus_ops # APIC cluster
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge
device lapic 0xACAC off end
end
end
device domain 0 on # PCI domain
device domain 0 on
ops x4x_pci_domain_ops # PCI domain
device pci 0.0 on end # Host Bridge
device pci 1.0 on end # PEG
device pci 6.0 off end # PEG 2

6
src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb
View File

@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/x4x # Northbridge
device cpu_cluster 0 on # APIC cluster
device cpu_cluster 0 on
ops x4x_cpu_bus_ops # APIC cluster
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge
device lapic 0xacac off end
end
end
device domain 0 on # PCI domain
device domain 0 on
ops x4x_pci_domain_ops # PCI domain
device pci 0.0 on end # Host Bridge
device pci 1.0 on end # PEG
device pci 2.0 off end # Integrated graphics controller

6
src/mainboard/asus/p5qc/variants/p5q_se/devicetree.cb
View File

@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/x4x # Northbridge
device cpu_cluster 0 on # APIC cluster
device cpu_cluster 0 on
ops x4x_cpu_bus_ops # APIC cluster
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge
device lapic 0xacac off end
end
end
device domain 0 on # PCI domain
device domain 0 on
ops x4x_pci_domain_ops # PCI domain
device pci 0.0 on end # Host Bridge
device pci 1.0 on end # PEG
device pci 2.0 off end # Integrated graphics controller

6
src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb
View File

@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/x4x # Northbridge
device cpu_cluster 0 on # APIC cluster
device cpu_cluster 0 on
ops x4x_cpu_bus_ops # APIC cluster
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge
device lapic 0xacac off end
end
end
device domain 0 on # PCI domain
device domain 0 on
ops x4x_pci_domain_ops # PCI domain
device pci 0.0 on end # Host Bridge
device pci 1.0 on end # PEG
device pci 2.0 off end # Integrated graphics controller

6
src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb
View File

@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/x4x # Northbridge
device cpu_cluster 0 on # APIC cluster
device cpu_cluster 0 on
ops x4x_cpu_bus_ops # APIC cluster
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge
device lapic 0xacac off end
end
end
device domain 0 on # PCI domain
device domain 0 on
ops x4x_pci_domain_ops # PCI domain
device pci 0.0 on end # Host Bridge
device pci 1.0 on end # PEG
device pci 2.0 off end # Integrated graphics controller

6
src/mainboard/asus/p5ql-em/devicetree.cb
View File

@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/x4x # Northbridge
device cpu_cluster 0 on # APIC cluster
device cpu_cluster 0 on
ops x4x_cpu_bus_ops # APIC cluster
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge
device lapic 0xacac off end
end
end
device domain 0 on # PCI domain
device domain 0 on
ops x4x_pci_domain_ops # PCI domain
device pci 0.0 on # Host Bridge
subsystemid 0x1043 0x8336
end

6
src/mainboard/asus/p5qpl-am/devicetree.cb
View File

@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/x4x # Northbridge
device cpu_cluster 0 on # APIC cluster
device cpu_cluster 0 on
ops x4x_cpu_bus_ops # APIC cluster
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge
device lapic 0xacac off end
end
end
device domain 0 on # PCI domain
device domain 0 on
ops x4x_pci_domain_ops # PCI domain
device pci 0.0 on end # Host Bridge
device pci 1.0 on end # PEG
device pci 2.0 on end # Integrated graphics controller

6
src/mainboard/foxconn/g41s-k/devicetree.cb
View File

@ -1,7 +1,8 @@
## SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/x4x # Northbridge
device cpu_cluster 0 on # APIC cluster
device cpu_cluster 0 on
ops x4x_cpu_bus_ops # APIC cluster
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge
device lapic 0xACAC off end
end
end
device domain 0 on # PCI domain
device domain 0 on
ops x4x_pci_domain_ops # PCI domain
device pci 0.0 on end # Host Bridge
device pci 1.0 on end # PEG
device pci 2.0 on end # Integrated graphics controller

6
src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
View File

@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/x4x # Northbridge
device cpu_cluster 0 on # APIC cluster
device cpu_cluster 0 on
ops x4x_cpu_bus_ops # APIC cluster
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge
device lapic 0xACAC off end
end
end
device domain 0 on # PCI domain
device domain 0 on
ops x4x_pci_domain_ops # PCI domain
subsystemid 0x1458 0x5000 inherit
device pci 0.0 on # Host Bridge
subsystemid 0x1458 0x5000

6
src/mainboard/intel/dg41wv/devicetree.cb
View File

@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/x4x # Northbridge
device cpu_cluster 0 on # APIC cluster
device cpu_cluster 0 on
ops x4x_cpu_bus_ops # APIC cluster
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge
device lapic 0xACAC off end
end
end
device domain 0 on # PCI domain
device domain 0 on
ops x4x_pci_domain_ops # PCI domain
subsystemid 0x1458 0x5000 inherit
device pci 0.0 on # Host Bridge
subsystemid 0x8086 0x5756

6
src/mainboard/intel/dg43gt/devicetree.cb
View File

@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/x4x # Northbridge
device cpu_cluster 0 on # APIC cluster
device cpu_cluster 0 on
ops x4x_cpu_bus_ops # APIC cluster
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge
device lapic 0xacac off end
end
end
device domain 0 on # PCI domain
device domain 0 on
ops x4x_pci_domain_ops # PCI domain
subsystemid 0x8086 0x0028 inherit
device pci 0.0 on end # Host Bridge
device pci 2.0 on end # Integrated graphics controller

6
src/mainboard/lenovo/thinkcentre_a58/devicetree.cb
View File

@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/x4x # Northbridge
device cpu_cluster 0 on # APIC cluster
device cpu_cluster 0 on
ops x4x_cpu_bus_ops # APIC cluster
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge
device lapic 0xACAC off end
end
end
device domain 0 on # PCI domain
device domain 0 on
ops x4x_pci_domain_ops # PCI domain
subsystemid 0x17aa 0x304f inherit
device pci 0.0 on end # Host Bridge
device pci 1.0 on end # PEG

14
src/northbridge/intel/x4x/northbridge.c
View File

@ -144,7 +144,7 @@ void northbridge_write_smram(u8 smram)
pci_write_config8(dev, D0F0_SMRAM, smram);
}
static struct device_operations pci_domain_ops = {
struct device_operations x4x_pci_domain_ops = {
.read_resources = mch_domain_read_resources,
.set_resources = mch_domain_set_resources,
.init = mch_domain_init,
@ -154,21 +154,12 @@ static struct device_operations pci_domain_ops = {
.acpi_name = northbridge_acpi_name,
};
static struct device_operations cpu_bus_ops = {
struct device_operations x4x_cpu_bus_ops = {
.read_resources = noop_read_resources,
.set_resources = noop_set_resources,
.init = mp_cpu_bus_init,
};
static void enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN)
dev->ops = &pci_domain_ops;
else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
dev->ops = &cpu_bus_ops;
}
static void hide_pci_fn(const int dev_bit_base, const struct device *dev)
{
if (!dev || dev->enabled)
@ -201,6 +192,5 @@ static void x4x_init(void *const chip_info)
struct chip_operations northbridge_intel_x4x_ops = {
CHIP_NAME("Intel 4-Series Northbridge")
.enable_dev = enable_dev,
.init = x4x_init,
};