From 1efc72affa03d25c728e0ecefb08239e725ffae9 Mon Sep 17 00:00:00 2001 From: Yidi Lin Date: Wed, 6 Apr 2016 16:28:06 +0800 Subject: [PATCH] google/oak: elm: Do not control SPI_LEVEL_ENABLE after elm-rev1 SPI level shifter is controlled by SRCLKENA0 after elm-rev1. We don't need to configure it in the bootloader. BUG=chrome-os-partner:51725 TEST=emerge-elm coreboot Change-Id: I01ec00965b87ae370b72d3c0521fb37268714cf8 Signed-off-by: Patrick Georgi Original-Commit-Id: 3234065e33c46bc2d67a96939422d318919d5e7a Original-Change-Id: Iafed0cd7562eb5921af6b17f73a067d469143e02 Original-Signed-off-by: Yidi Lin Original-Reviewed-on: https://chromium-review.googlesource.com/337421 Original-Reviewed-by: Julius Werner Reviewed-on: https://review.coreboot.org/14694 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/google/oak/bootblock.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c index 325889cbb3..04a3a550ec 100644 --- a/src/mainboard/google/oak/bootblock.c +++ b/src/mainboard/google/oak/bootblock.c @@ -81,7 +81,8 @@ void bootblock_mainboard_init(void) nor_set_gpio_pinmux(); /* SPI_LEVEL_ENABLE: Enable 1.8V to 3.3V level shifter for EC SPI bus */ - if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4) + if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4 && + board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 8) gpio_output(PAD_SRCLKENAI2, 1); /* Init i2c bus 2 Timing register for TPM */