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mediatek: Map SRAM as secure and cached memory 

This patch changes the mapping of SRAM from non-secure to secure.
Without this patch, mmu_config_range() can not work when MMU is
enabled. The new config is still in non-secure cache since TTB section
is allocated in SRAM which is mapped as non-secure.

BUG=b:80501386
TEST=Boots correctly on Kukui and Elm

Change-Id: Ia5b8716cfcca64d1d716a177225ea2f7ac2920a6
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Tristan Shieh 2018-08-09 15:14:15 +08:00 committed by Patrick Georgi
parent 4cb8ac234b
commit 1efe2578c0
3 changed files with 17 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/soc/mediatek/common/include/soc/mmu_operations.h
View File

@ -19,10 +19,11 @@
#include <arch/mmu.h>
enum {
DEV_MEM = MA_DEV | MA_S | MA_RW,
CACHED_MEM = MA_MEM | MA_NS | MA_RW,
SECURE_MEM = MA_MEM | MA_S | MA_RW,
UNCACHED_MEM = MA_MEM | MA_NS | MA_RW | MA_MEM_NC,
DEV_MEM = MA_DEV | MA_S | MA_RW,
SECURE_CACHED_MEM = MA_MEM | MA_S | MA_RW,
SECURE_UNCACHED_MEM = MA_MEM | MA_S | MA_RW | MA_MEM_NC,
NONSECURE_CACHED_MEM = MA_MEM | MA_NS | MA_RW,
NONSECURE_UNCACHED_MEM = MA_MEM | MA_NS | MA_RW | MA_MEM_NC,
};
extern unsigned char _sram_l2c[];

17
src/soc/mediatek/common/mmu_operations.c
View File

@ -25,17 +25,22 @@ void mtk_mmu_init(void)
{
mmu_init();
/* Set 0x0 to the end of 2GB dram address as device memory */
mmu_config_range((void *)0, (uintptr_t)_dram + 2U * GiB, DEV_MEM);
/*
* Set 0x0 to 4GB address as device memory. We want to config IO_PHYS
* address to DEV_MEM, and map a proper range of dram for the memory
* test during calibration.
*/
mmu_config_range((void *)0, (uintptr_t)4U * GiB, DEV_MEM);
/* SRAM is cached */
mmu_config_range(_sram, _sram_size, CACHED_MEM);
mmu_config_range(_sram, _sram_size, SECURE_CACHED_MEM);
/* L2C SRAM is cached */
mmu_config_range(_sram_l2c, _sram_l2c_size, CACHED_MEM);
mmu_config_range(_sram_l2c, _sram_l2c_size, SECURE_CACHED_MEM);
/* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */
mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM);
mmu_config_range(_dma_coherent, _dma_coherent_size,
SECURE_UNCACHED_MEM);
mmu_enable();
}
@ -43,7 +48,7 @@ void mtk_mmu_init(void)
void mtk_mmu_after_dram(void)
{
/* Map DRAM as cached now that it's up and running */
mmu_config_range(_dram, (uintptr_t)sdram_size(), CACHED_MEM);
mmu_config_range(_dram, (uintptr_t)sdram_size(), NONSECURE_CACHED_MEM);
mtk_soc_after_dram();
}

2
src/soc/mediatek/mt8173/mmu_operations.c
View File

@ -23,7 +23,7 @@
void mtk_soc_after_dram(void)
{
mmu_config_range(_dram_dma, _dram_dma_size, UNCACHED_MEM);
mmu_config_range(_dram_dma, _dram_dma_size, NONSECURE_UNCACHED_MEM);
mtk_mmu_disable_l2c_sram();
}