sb/intel/ibexpeak: Copy the sandybridge bootblock.c file
This allows to port C_ENVIRONMENT_BOOTBLOCK to sandybridge separately from nehalem. Change-Id: If3c6619cf22d1e2995eb19823b0f3f969d252b3b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -53,7 +53,7 @@ config DRAM_RESET_GATE_GPIO
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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default "southbridge/intel/bd82x6x/bootblock.c"
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default "southbridge/intel/ibexpeak/bootblock.c"
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config SERIRQ_CONTINUOUS_MODE
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bool
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@ -0,0 +1,77 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/pci_ops.h>
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#include "pch.h"
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/*
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* Enable Prefetching and Caching.
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*/
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static void enable_spi_prefetch(void)
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{
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u8 reg8;
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pci_devfn_t dev = PCH_LPC_DEV;
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reg8 = pci_read_config8(dev, BIOS_CNTL);
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reg8 &= ~(3 << 2);
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reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
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pci_write_config8(dev, BIOS_CNTL, reg8);
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}
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static void enable_port80_on_lpc(void)
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{
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pci_devfn_t dev = PCH_LPC_DEV;
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/* Enable port 80 POST on LPC */
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pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
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#if 0
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RCBA32(GCS) &= (~0x04);
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#else
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volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS);
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u32 reg32 = *gcs;
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reg32 = reg32 & ~0x04;
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*gcs = reg32;
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#endif
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}
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static void set_spi_speed(void)
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{
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u32 fdod;
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u8 ssfc;
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/* Observe SPI Descriptor Component Section 0 */
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RCBA32(0x38b0) = 0x1000;
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/* Extract the Write/Erase SPI Frequency from descriptor */
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fdod = RCBA32(0x38b4);
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fdod >>= 24;
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fdod &= 7;
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/* Set Software Sequence frequency to match */
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ssfc = RCBA8(0x3893);
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ssfc &= ~7;
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ssfc |= fdod;
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RCBA8(0x3893) = ssfc;
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}
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static void bootblock_southbridge_init(void)
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{
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enable_spi_prefetch();
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enable_port80_on_lpc();
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set_spi_speed();
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/* Enable upper 128bytes of CMOS */
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RCBA32(RC) = (1 << 2);
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}
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