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sb/intel/ibexpeak: Copy the sandybridge bootblock.c file 

This allows to port C_ENVIRONMENT_BOOTBLOCK to sandybridge separately
from nehalem.

Change-Id: If3c6619cf22d1e2995eb19823b0f3f969d252b3b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans 2019-06-04 09:46:36 +02:00 committed by Felix Held
parent 05284b64d0
commit 1f12772d19
2 changed files with 78 additions and 1 deletions
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2
src/southbridge/intel/ibexpeak/Kconfig
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@ -53,7 +53,7 @@ config DRAM_RESET_GATE_GPIO
config BOOTBLOCK_SOUTHBRIDGE_INIT config BOOTBLOCK_SOUTHBRIDGE_INIT
string string
default "southbridge/intel/bd82x6x/bootblock.c" default "southbridge/intel/ibexpeak/bootblock.c"
config SERIRQ_CONTINUOUS_MODE config SERIRQ_CONTINUOUS_MODE
bool bool

77
src/southbridge/intel/ibexpeak/bootblock.c Normal file
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@ -0,0 +1,77 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/pci_ops.h>
#include "pch.h"
/*
* Enable Prefetching and Caching.
*/
static void enable_spi_prefetch(void)
{
u8 reg8;
pci_devfn_t dev = PCH_LPC_DEV;
reg8 = pci_read_config8(dev, BIOS_CNTL);
reg8 &= ~(3 << 2);
reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
pci_write_config8(dev, BIOS_CNTL, reg8);
}
static void enable_port80_on_lpc(void)
{
pci_devfn_t dev = PCH_LPC_DEV;
/* Enable port 80 POST on LPC */
pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
#if 0
RCBA32(GCS) &= (~0x04);
#else
volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS);
u32 reg32 = *gcs;
reg32 = reg32 & ~0x04;
*gcs = reg32;
#endif
}
static void set_spi_speed(void)
{
u32 fdod;
u8 ssfc;
/* Observe SPI Descriptor Component Section 0 */
RCBA32(0x38b0) = 0x1000;
/* Extract the Write/Erase SPI Frequency from descriptor */
fdod = RCBA32(0x38b4);
fdod >>= 24;
fdod &= 7;
/* Set Software Sequence frequency to match */
ssfc = RCBA8(0x3893);
ssfc &= ~7;
ssfc |= fdod;
RCBA8(0x3893) = ssfc;
}
static void bootblock_southbridge_init(void)
{
enable_spi_prefetch();
enable_port80_on_lpc();
set_spi_speed();
/* Enable upper 128bytes of CMOS */
RCBA32(RC) = (1 << 2);
}