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mb/siemens/{mc_apl1,...,mc_apl5}: Reduce eMMC bus speed mode 

We need to reduce the eMMC bus speed for these Apollo Lake mainboards
because of a limitation on Intel side for industry use cases.

Change-Id: Ide6a1a302001c0752d149bfdab175a27c8f8cc35
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Mario Scheithauer 2019-07-10 13:15:54 +02:00 committed by Martin Roth
parent badbcde542
commit 1f21a96c84
5 changed files with 5 additions and 5 deletions
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2
src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
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@ -44,7 +44,7 @@ chip soc/intel/apollolake
register "emmc_rx_cmd_data_cntl2" = "0x10008" register "emmc_rx_cmd_data_cntl2" = "0x10008"
# 0:HS400(Default), 1:HS200, 2:DDR50 # 0:HS400(Default), 1:HS200, 2:DDR50
register "emmc_host_max_speed" = "2" register "emmc_host_max_speed" = "1"
# Intel Common SoC Config # Intel Common SoC Config
#+-------------------+---------------------------+ #+-------------------+---------------------------+

2
src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
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@ -45,7 +45,7 @@ chip soc/intel/apollolake
register "emmc_rx_cmd_data_cntl2" = "0x10008" register "emmc_rx_cmd_data_cntl2" = "0x10008"
# 0:HS400(Default), 1:HS200, 2:DDR50 # 0:HS400(Default), 1:HS200, 2:DDR50
register "emmc_host_max_speed" = "2" register "emmc_host_max_speed" = "1"
# Enable Vtd feature # Enable Vtd feature
register "enable_vtd" = "1" register "enable_vtd" = "1"

2
src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
View File

@ -44,7 +44,7 @@ chip soc/intel/apollolake
register "emmc_rx_cmd_data_cntl2" = "0x10008" register "emmc_rx_cmd_data_cntl2" = "0x10008"
# 0:HS400(Default), 1:HS200, 2:DDR50 # 0:HS400(Default), 1:HS200, 2:DDR50
register "emmc_host_max_speed" = "2" register "emmc_host_max_speed" = "1"
device domain 0 on device domain 0 on
device pci 00.0 on end # - Host Bridge device pci 00.0 on end # - Host Bridge

2
src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
View File

@ -45,7 +45,7 @@ chip soc/intel/apollolake
register "emmc_rx_cmd_data_cntl2" = "0x10008" register "emmc_rx_cmd_data_cntl2" = "0x10008"
# 0:HS400(Default), 1:HS200, 2:DDR50 # 0:HS400(Default), 1:HS200, 2:DDR50
register "emmc_host_max_speed" = "2" register "emmc_host_max_speed" = "1"
device domain 0 on device domain 0 on
device pci 00.0 on end # - Host Bridge device pci 00.0 on end # - Host Bridge

2
src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
View File

@ -44,7 +44,7 @@ chip soc/intel/apollolake
register "emmc_rx_cmd_data_cntl2" = "0x10008" register "emmc_rx_cmd_data_cntl2" = "0x10008"
# 0:HS400(Default), 1:HS200, 2:DDR50 # 0:HS400(Default), 1:HS200, 2:DDR50
register "emmc_host_max_speed" = "2" register "emmc_host_max_speed" = "1"
# Enable Vtd feature # Enable Vtd feature
register "enable_vtd" = "1" register "enable_vtd" = "1"