soc/mediatek: Fix typos in comments
Also add missing whitespace. Change-Id: I3361122d5232072e68d018e84219a262acf34001 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
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@ -69,7 +69,7 @@ static inline s32 pwrap_write_nochk(u16 addr, u16 wdata)
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return pwrap_wacs2(1, addr, wdata, 0, 0);
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}
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/* dewrapper defaule value */
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/* dewrapper default value */
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enum {
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DEFAULT_VALUE_READ_TEST = 0x5aa5,
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WRITE_TEST_VALUE = 0xa55a
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@ -81,7 +81,7 @@ enum {
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TIMEOUT_WAIT_IDLE_US = 255
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};
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/* manual commnd */
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/* manual command */
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enum {
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OP_WR = 0x1,
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OP_CSH = 0x0,
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@ -450,7 +450,7 @@ static void dramc_set_mrs_value(int channel, int rank,
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mrs_write(channel, rank, sdram_params->mrs_set.mrs_63, 10);
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/* MR10 -> ZQ Init, tZQINIT>=1us */
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mrs_write(channel, rank, sdram_params->mrs_set.mrs_10, 1);
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/* MR3 driving stregth set to max */
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/* MR3 driving strength set to max */
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mrs_write(channel, rank, sdram_params->mrs_set.mrs_3, 1);
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/* MR1 */
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mrs_write(channel, rank, sdram_params->mrs_set.mrs_1, 1);
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@ -971,9 +971,9 @@ void perbit_window_cal(u32 channel, u8 type)
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dqdqs_perbit_dly[i].best_last_dqsdly_pass = -2;
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}
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/* 1. delay DQ,find the pass widnow (left boundary)
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/* 1. delay DQ,find the pass window (left boundary)
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* 2. delay DQS find the pass window (right boundary)
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* 3. find the best DQ / DQS to satify the middle value
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* 3. find the best DQ / DQS to satisfy the middle value
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* of the overall pass window per bit
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* 4. set DQS delay to the max per byte, delay DQ to de-skew
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*/
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@ -148,7 +148,7 @@ size_t sdram_size(void)
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9;
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/* check if row address */
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/*00 is 13 bits, 01 is 14 bits, 10 is 15bits, 11 is 16 bits */
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/* 00 is 13 bits, 01 is 14 bits, 10 is 15bits, 11 is 16 bits */
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bit_counter += ((value & ROW_ADDR_BITS_MASK) >> ROW_ADDR_BITS_SHIFT) +
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13;
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@ -159,7 +159,7 @@ size_t sdram_size(void)
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/* add bank address bit, LPDDR3 is 8 banks =2^3 */
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bit_counter += 3;
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/*transfor bits to bytes */
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/* transform bits to bytes */
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return ((size_t)1 << (bit_counter - 3));
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}
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@ -125,7 +125,7 @@ struct mt8173_pwrap_regs {
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check_member(mt8173_pwrap_regs, dcm_dbc_prd, 0x148);
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/* dewrapper regsister */
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/* dewrapper register */
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enum {
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DEW_EVENT_OUT_EN = DEW_BASE + 0x0,
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DEW_DIO_EN = DEW_BASE + 0x2,
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@ -201,7 +201,7 @@ static void mt6391_init_setting(void)
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pwrap_write_field(PMIC_RG_VSRMCA15_CON8, 0x17, 0x7F, 0);
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/* [6:0]: VSRMCA15_VOSEL_SLEEP; Sleep mode setting on */
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pwrap_write_field(PMIC_RG_VSRMCA15_CON11, 0x00, 0x7F, 0);
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/* [8:8]: VSRMCA15_VSLEEP_EN; set sleep mode referenc */
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/* [8:8]: VSRMCA15_VSLEEP_EN; set sleep mode reference */
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pwrap_write_field(PMIC_RG_VSRMCA15_CON18, 0x1, 0x1, 8);
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/* [5:4]: VSRMCA15_VOSEL_TRANS_EN; rising & falling e */
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pwrap_write_field(PMIC_RG_VSRMCA15_CON18, 0x3, 0x3, 4);
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@ -359,7 +359,7 @@ static void mt6391_init_setting(void)
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pwrap_write_field(PMIC_RG_VDRM_CON9, 0x43, 0x7F, 0);
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pwrap_write_field(PMIC_RG_VDRM_CON10, 0x43, 0x7F, 0);
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/* 26M clock amplitute adjust */
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/* 26M clock amplitude adjust */
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pwrap_write_field(PMIC_RG_DCXO_ANALOG_CON1, 0x0, 0x3, 2);
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pwrap_write_field(PMIC_RG_DCXO_ANALOG_CON1, 0x1, 0x3, 11);
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@ -274,7 +274,7 @@ static int spm_load_firmware(enum dyna_load_pcm_index index,
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offset += copy_size;
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/* version */
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/* The termintating character should be contained in the spm binary */
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/* The terminating character should be contained in the spm binary */
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assert(spm_bin[file_size - 1] == '\0');
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assert(offset < file_size);
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printk(BIOS_DEBUG, "SPM: version = %s\n", spm_bin + offset);
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