slippy: remove FUI support
There's no reason to keep maintaining support on this mainboard, since nobody has one. Change-Id: I5c7c8ea4640170ba231fec82a94a54ee1876b845 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/180503 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit e291d82acbc8bf0d1372e11ac100a7dd340a0040) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6913 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Ronald G. Minnich
Isaac Christensen
parent
1101a71219
commit
1f279b68b6
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@ -21,7 +21,6 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
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romstage-y += chromeos.c
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romstage-y += chromeos.c
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ramstage-y += chromeos.c
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ramstage-y += chromeos.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += gma.c i915io.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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@ -1,388 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <string.h>
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#include <stdlib.h>
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#include <device/device.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <delay.h>
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#include <pc80/mc146818rtc.h>
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <arch/interrupt.h>
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#include <boot/coreboot_tables.h>
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#include <smbios.h>
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#include <device/pci.h>
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#include <ec/google/chromeec/ec.h>
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#include <cbfs_core.h>
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#include <cpu/x86/tsc.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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#include <edid.h>
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#include <drivers/intel/gma/i915.h>
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#include "mainboard.h"
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/*
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* Here is the rough outline of how we bring up the display:
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* 1. Upon power-on Sink generates a hot plug detection pulse thru HPD
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* 2. Source determines video mode by reading DPCD receiver capability field
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* (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD
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* 0000Dh).
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* 3. Sink replies DPCD receiver capability field.
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* 4. Source starts EDID read thru I2C-over-AUX.
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* 5. Sink replies EDID thru I2C-over-AUX.
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* 6. Source determines link configuration, such as MAX_LINK_RATE and
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* MAX_LANE_COUNT. Source also determines which type of eDP Authentication
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* method to use and writes DPCD link configuration field (DPCD 00100h to
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* 0010Ah) including eDP configuration set (DPCD 0010Ah).
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* 7. Source starts link training. Sink does clock recovery and equalization.
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* 8. Source reads DPCD link status field (DPCD 00200h to 0020Bh).
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* 9. Sink replies DPCD link status field. If main link is not stable, Source
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* repeats Step 7.
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* 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video
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* parameters and recovers stream clock.
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* 11. Source sends video data.
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*/
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/* how many bytes do we need for the framebuffer?
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* Well, this gets messy. To get an exact answer, we have
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* to ask the panel, but we'd rather zero the memory
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* and set up the gtt while the panel powers up. So,
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* we take a reasonable guess, secure in the knowledge that the
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* MRC has to overestimate the number of bytes used.
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* 8 MiB is a very safe guess. There may be a better way later, but
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* fact is, the initial framebuffer is only very temporary. And taking
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* a little long is ok; this is done much faster than the AUX
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* channel is ready for IO.
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*/
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#define FRAME_BUFFER_BYTES (8*MiB)
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/* how many 4096-byte pages do we need for the framebuffer?
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* There are hard ways to get this, and easy ways:
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* there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096
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* on this chip (and in fact every Intel graphics chip we've seen).
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*/
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#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096))
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static unsigned int *mmio;
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static unsigned int graphics;
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static unsigned int physbase;
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void ug1(int);
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void ug2(int);
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void ug22(int);
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void ug3(int);
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/* GTT is the Global Translation Table for the graphics pipeline.
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* It is used to translate graphics addresses to physical
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* memory addresses. As in the CPU, GTTs map 4K pages.
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* The setgtt function adds a further bit of flexibility:
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* it allows you to set a range (the first two parameters) to point
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* to a physical address (third parameter);the physical address is
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* incremented by a count (fourth parameter) for each GTT in the
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* range.
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* Why do it this way? For ultrafast startup,
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* we can point all the GTT entries to point to one page,
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* and set that page to 0s:
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* memset(physbase, 0, 4096);
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* setgtt(0, 4250, physbase, 0);
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* this takes about 2 ms, and is a win because zeroing
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* the page takes a up to 200 ms.
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* This call sets the GTT to point to a linear range of pages
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* starting at physbase.
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*/
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#define GTT_PTE_BASE (2 << 20)
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static void
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setgtt(int start, int end, unsigned long base, int inc)
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{
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int i;
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for(i = start; i < end; i++){
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u32 word = base + i*inc;
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/* note: we've confirmed by checking
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* the values that mrc does no
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* useful setup before we run this.
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*/
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gtt_write(GTT_PTE_BASE + i * 4, word|1);
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gtt_read(GTT_PTE_BASE + i * 4);
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}
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}
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static int i915_init_done = 0;
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/* fill the palette. */
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static void palette(void)
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{
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int i;
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unsigned long color = 0;
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for(i = 0; i < 256; i++, color += 0x010101){
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gtt_write(_LGC_PALETTE_A + (i<<2),color);
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}
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}
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void dp_init_dim_regs(struct intel_dp *dp);
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void dp_init_dim_regs(struct intel_dp *dp)
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{
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struct edid *edid = &(dp->edid);
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dp->bytes_per_pixel = edid->framebuffer_bits_per_pixel / 8;
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dp->stride = edid->bytes_per_line;
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dp->htotal = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16);
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dp->hblank = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16);
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dp->hsync = (edid->ha + edid->hso - 1) |
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((edid->ha + edid->hso + edid->hspw - 1) << 16);
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dp->vtotal = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16);
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dp->vblank = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16);
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dp->vsync = (edid->va + edid->vso - 1) |
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((edid->va + edid->vso + edid->vspw - 1) << 16);
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/* PIPEASRC is wid-1 x ht-1 */
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dp->pipesrc = (edid->ha-1)<<16 | (edid->va-1);
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dp->pfa_pos = 0;
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dp->pfa_ctl = 0x80800000;
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dp->pfa_sz = (edid->ha << 16) | (edid->va);
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dp->flags = intel_ddi_calc_transcoder_flags(3 * 6, /* bits per color is 6 */
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dp->port,
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dp->pipe,
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dp->type,
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dp->lane_count,
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dp->pfa_sz,
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dp->edid.phsync == '+'?1:0,
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dp->edid.pvsync == '+'?1:0);
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dp->transcoder = intel_ddi_get_transcoder(dp->port,
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dp->pipe);
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intel_dp_compute_m_n(dp->pipe_bits_per_pixel,
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dp->lane_count,
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dp->edid.pixel_clock,
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dp->edid.link_clock,
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&dp->m_n);
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printk(BIOS_SPEW, "dp->stride = 0x%08x\n",dp->stride);
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printk(BIOS_SPEW, "dp->htotal = 0x%08x\n", dp->htotal);
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printk(BIOS_SPEW, "dp->hblank = 0x%08x\n", dp->hblank);
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printk(BIOS_SPEW, "dp->hsync = 0x%08x\n", dp->hsync);
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printk(BIOS_SPEW, "dp->vtotal = 0x%08x\n", dp->vtotal);
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printk(BIOS_SPEW, "dp->vblank = 0x%08x\n", dp->vblank);
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printk(BIOS_SPEW, "dp->vsync = 0x%08x\n", dp->vsync);
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printk(BIOS_SPEW, "dp->pipesrc = 0x%08x\n", dp->pipesrc);
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printk(BIOS_SPEW, "dp->pfa_pos = 0x%08x\n", dp->pfa_pos);
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printk(BIOS_SPEW, "dp->pfa_ctl = 0x%08x\n", dp->pfa_ctl);
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printk(BIOS_SPEW, "dp->pfa_sz = 0x%08x\n", dp->pfa_sz);
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printk(BIOS_SPEW, "dp->link_m = 0x%08x\n", dp->m_n.link_m);
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printk(BIOS_SPEW, "dp->link_n = 0x%08x\n", dp->m_n.link_n);
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printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m);
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printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", dp->m_n.gmch_m);
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printk(BIOS_SPEW, "0x6f034 = 0x%08x\n", dp->m_n.gmch_n);
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printk(BIOS_SPEW, "dp->flags = 0x%08x\n", dp->flags);
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}
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void mainboard_train_link(struct intel_dp *intel_dp)
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{
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u8 read_val;
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u8 link_status[DP_LINK_STATUS_SIZE];
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gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE);
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gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH |0x80000011);
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intel_dp_get_training_pattern(intel_dp, &read_val);
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intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
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intel_dp_get_lane_count(intel_dp, &read_val);
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intel_dp_set_training_lane0(intel_dp, DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0);
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intel_dp_get_link_status(intel_dp, link_status);
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gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT2);
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intel_dp_get_training_pattern(intel_dp, &read_val);
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intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
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intel_dp_get_link_status(intel_dp, link_status);
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intel_dp_get_lane_align_status(intel_dp, &read_val);
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intel_dp_get_training_pattern(intel_dp, &read_val);
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intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
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}
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#define TEST_GFX 0
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#if TEST_GFX
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static void test_gfx(struct intel_dp *dp)
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{
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int i;
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/* This is a sanity test code which fills the screen with two bands --
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green and blue. It is very useful to ensure all the initializations
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are made right. Thus, to be used only for testing, not otherwise
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*/
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for (i = 0; i < (dp->edid.va - 4); i++) {
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u32 *l;
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int j;
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u32 tcolor = 0x0ff;
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for (j = 0; j < (dp->edid.ha-4); j++) {
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if (j == (dp->edid.ha/2)) {
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tcolor = 0xff00;
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}
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l = (u32*)(graphics + i * dp->stride + j * sizeof(tcolor));
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memcpy(l,&tcolor,sizeof(tcolor));
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}
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}
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}
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#else
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static void test_gfx(struct intel_dp *dp) {}
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#endif
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void mainboard_set_port_clk_dp(struct intel_dp *intel_dp)
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{
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u32 ddi_pll_sel = 0;
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switch (intel_dp->link_bw) {
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case DP_LINK_BW_1_62:
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ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
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break;
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case DP_LINK_BW_2_7:
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ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
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break;
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case DP_LINK_BW_5_4:
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ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
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break;
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default:
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printk(BIOS_ERR, "invalid link bw %d\n", intel_dp->link_bw);
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return;
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}
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gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel);
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}
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int i915lightup(unsigned int pphysbase, unsigned int pmmio,
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unsigned int pgfx, unsigned int init_fb)
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{
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int must_cycle_power = 0;
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struct intel_dp adp, *dp = &adp;
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int i;
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int edid_ok;
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int pixels = FRAME_BUFFER_BYTES/64;
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mmio = (void *)pmmio;
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physbase = pphysbase;
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graphics = pgfx;
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printk(BIOS_SPEW,
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"i915lightup: graphics %p mmio %p"
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"physbase %08x\n",
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(void *)graphics, mmio, physbase);
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void runio(struct intel_dp *dp);
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void runlinux(struct intel_dp *dp);
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dp->gen = 8; // This is gen 8 which we believe is Haswell
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dp->is_haswell = 1;
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dp->DP = 0x2;
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/* These values are used for training the link */
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dp->lane_count = 2;
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|
||||||
dp->link_bw = DP_LINK_BW_2_7;
|
|
||||||
dp->panel_power_down_delay = 600;
|
|
||||||
dp->panel_power_up_delay = 200;
|
|
||||||
dp->panel_power_cycle_delay = 600;
|
|
||||||
dp->pipe = PIPE_A;
|
|
||||||
dp->port = PORT_A;
|
|
||||||
dp->plane = PLANE_A;
|
|
||||||
dp->clock = 160000;
|
|
||||||
dp->pipe_bits_per_pixel = 32;
|
|
||||||
dp->type = INTEL_OUTPUT_EDP;
|
|
||||||
dp->output_reg = DP_A;
|
|
||||||
/* observed from YABEL. */
|
|
||||||
dp->aux_clock_divider = 0xe1;
|
|
||||||
dp->precharge = 3;
|
|
||||||
|
|
||||||
/* 1. Normal mode: Set the first page to zero and make
|
|
||||||
all GTT entries point to the same page
|
|
||||||
2. Developer/Recovery mode: We do not zero out all
|
|
||||||
the pages pointed to by GTT in order to avoid wasting time */
|
|
||||||
if (init_fb)
|
|
||||||
setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
|
|
||||||
else {
|
|
||||||
setgtt(0, FRAME_BUFFER_PAGES, physbase, 0);
|
|
||||||
memset((void*)graphics, 0, 4096);
|
|
||||||
}
|
|
||||||
|
|
||||||
dp->address = 0x50;
|
|
||||||
|
|
||||||
if ( !intel_dp_get_dpcd(dp) )
|
|
||||||
goto fail;
|
|
||||||
|
|
||||||
intel_dp_i2c_aux_ch(dp, MODE_I2C_WRITE, 0, NULL);
|
|
||||||
for(dp->edidlen = i = 0; i < sizeof(dp->rawedid); i++){
|
|
||||||
if (intel_dp_i2c_aux_ch(dp, MODE_I2C_READ,
|
|
||||||
0x50, &dp->rawedid[i]) < 0)
|
|
||||||
break;
|
|
||||||
dp->edidlen++;
|
|
||||||
}
|
|
||||||
|
|
||||||
edid_ok = decode_edid(dp->rawedid, dp->edidlen, &dp->edid);
|
|
||||||
printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok);
|
|
||||||
|
|
||||||
dp->edid.link_clock = intel_dp_bw_code_to_link_rate(dp->link_bw);
|
|
||||||
|
|
||||||
printk(BIOS_SPEW, "pixel_clock is %i, link_clock is %i\n",dp->edid.pixel_clock, dp->edid.link_clock);
|
|
||||||
|
|
||||||
dp_init_dim_regs(dp);
|
|
||||||
|
|
||||||
intel_ddi_set_pipe_settings(dp);
|
|
||||||
|
|
||||||
runio(dp);
|
|
||||||
|
|
||||||
palette();
|
|
||||||
|
|
||||||
pixels = dp->edid.ha * (dp->edid.va-4) * 4;
|
|
||||||
printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.ha, dp->edid.va);
|
|
||||||
|
|
||||||
test_gfx(dp);
|
|
||||||
|
|
||||||
set_vbe_mode_info_valid(&dp->edid, graphics);
|
|
||||||
i915_init_done = 1;
|
|
||||||
return i915_init_done;
|
|
||||||
|
|
||||||
fail:
|
|
||||||
printk(BIOS_SPEW, "Graphics could not be started;");
|
|
||||||
if (0 && must_cycle_power){
|
|
||||||
printk(BIOS_SPEW, "Turn off power and wait ...");
|
|
||||||
gtt_write(PCH_PP_CONTROL,0xabcd0000);
|
|
||||||
udelay(600000);
|
|
||||||
gtt_write(PCH_PP_CONTROL,0xabcd000f);
|
|
||||||
}
|
|
||||||
printk(BIOS_SPEW, "Returning.\n");
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
@ -1,135 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright 2013 Google Inc.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* This code was originally generated using an i915tool program. It has been
|
|
||||||
* improved by hand.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <stdint.h>
|
|
||||||
#include <console/console.h>
|
|
||||||
#include <delay.h>
|
|
||||||
#include <drivers/intel/gma/i915.h>
|
|
||||||
#include <arch/io.h>
|
|
||||||
#include "mainboard.h"
|
|
||||||
|
|
||||||
/* these variables will be removed when the proper support is finished in src/drivers/intel/gma/intel_dp.c */
|
|
||||||
int index;
|
|
||||||
u32 auxout;
|
|
||||||
u8 auxin[20];
|
|
||||||
u8 msg[32];
|
|
||||||
|
|
||||||
/* this function will either be renamed or subsumed into ./gma.c:i915_lightup */
|
|
||||||
void runio(struct intel_dp *dp);
|
|
||||||
|
|
||||||
void runio(struct intel_dp *dp)
|
|
||||||
{
|
|
||||||
u8 read_val;
|
|
||||||
|
|
||||||
intel_dp_wait_panel_power_control(0xabcd0008);
|
|
||||||
|
|
||||||
/* vbios spins at this point. Some haswell weirdness? */
|
|
||||||
intel_dp_wait_panel_power_control(0xabcd0008);
|
|
||||||
|
|
||||||
/* This should be a function like intel_panel_enable_backlight
|
|
||||||
However, we are not sure how the value 0x3a9 comes up.
|
|
||||||
It has to do something with PWM frequency */
|
|
||||||
gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
|
|
||||||
gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
|
|
||||||
gtt_write(BLC_PWM_PCH_CTL1,BLM_PCH_PWM_ENABLE);
|
|
||||||
|
|
||||||
gtt_write(DEIIR,0x00008000);
|
|
||||||
intel_dp_wait_reg(DEIIR, 0x00000000);
|
|
||||||
|
|
||||||
gtt_write(DSPSTRIDE(dp->plane),dp->stride);
|
|
||||||
|
|
||||||
intel_dp_sink_dpms(dp, 0);
|
|
||||||
|
|
||||||
intel_dp_get_max_downspread(dp, &read_val);
|
|
||||||
|
|
||||||
intel_dp_set_m_n_regs(dp);
|
|
||||||
|
|
||||||
intel_dp_set_resolution(dp);
|
|
||||||
|
|
||||||
gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
|
|
||||||
gtt_write(PIPECONF(dp->transcoder),0x00000000);
|
|
||||||
gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000);
|
|
||||||
|
|
||||||
mainboard_set_port_clk_dp(dp);
|
|
||||||
gtt_write(DSPSTRIDE(dp->plane),dp->stride);
|
|
||||||
gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_RGBX888);
|
|
||||||
gtt_write(DEIIR,0x00000080);
|
|
||||||
|
|
||||||
gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags);
|
|
||||||
gtt_write(PIPECONF(dp->transcoder),PIPECONF_ENABLE|PIPECONF_DITHER_EN);
|
|
||||||
|
|
||||||
intel_dp_wait_panel_power_control(0xabcd000a);
|
|
||||||
|
|
||||||
/* what is this doing? Not sure yet. */
|
|
||||||
intel_dp_i2c_write(dp, 0x0);
|
|
||||||
intel_dp_i2c_read(dp, &read_val);
|
|
||||||
intel_dp_i2c_write(dp, 0x04);
|
|
||||||
intel_dp_i2c_read(dp, &read_val);
|
|
||||||
intel_dp_i2c_write(dp, 0x7e);
|
|
||||||
intel_dp_i2c_read(dp, &read_val);
|
|
||||||
|
|
||||||
/* this needs to be a call to a function */
|
|
||||||
gtt_write(DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x00000091);
|
|
||||||
gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE);
|
|
||||||
gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x80040091);
|
|
||||||
|
|
||||||
/* we may need to move these *after* power well power up and *before* PCH_PP_CONTROL in gma.c */
|
|
||||||
gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x0001000a);
|
|
||||||
gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x07d0000a);
|
|
||||||
|
|
||||||
intel_dp_set_bw(dp);
|
|
||||||
intel_dp_set_lane_count(dp);
|
|
||||||
|
|
||||||
mainboard_train_link(dp);
|
|
||||||
|
|
||||||
/* need a function: intel_ddi_set_tp or similar */
|
|
||||||
gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_IDLE);
|
|
||||||
gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_NORMAL);
|
|
||||||
|
|
||||||
gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
|
|
||||||
gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
|
|
||||||
gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
|
|
||||||
|
|
||||||
/* some of this is not needed. */
|
|
||||||
gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE );
|
|
||||||
|
|
||||||
gtt_write(SDEIIR,0x00000000);
|
|
||||||
gtt_write(DEIIR,0x00000000);
|
|
||||||
gtt_write(DEIIR,0x00008000);
|
|
||||||
intel_dp_wait_reg(DEIIR, 0x00000000);
|
|
||||||
|
|
||||||
gtt_write(DSPSTRIDE(dp->plane),dp->stride);
|
|
||||||
gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
|
|
||||||
|
|
||||||
gtt_write(DEIIR,0x00000080);
|
|
||||||
intel_dp_wait_reg(DEIIR, 0x00000000);
|
|
||||||
|
|
||||||
gtt_write(DSPSTRIDE(dp->plane),dp->stride);
|
|
||||||
gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_RGBX888);
|
|
||||||
|
|
||||||
gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON);
|
|
||||||
|
|
||||||
gtt_write(SDEIIR,0x00000000);
|
|
||||||
gtt_write(SDEIIR,0x00000000);
|
|
||||||
gtt_write(DEIIR,0x00000000);
|
|
||||||
}
|
|
||||||
Loading…
Reference in New Issue