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sb/intel/common: Make RCBA manipulation MACROs common 

No Change in BUILD_TIMELESS.

Change-Id: I634526269d45ebdc6c31cdc28d9ec846b397211d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Arthur Heymans 2018-06-12 23:48:30 +02:00 committed by Patrick Georgi
parent 58a8953793
commit 1f2ae91074
3 changed files with 43 additions and 32 deletions
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17
src/southbridge/intel/bd82x6x/pch.h
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@ -45,11 +45,7 @@
#define DEFAULT_GPIOBASE 0x0480
#define DEFAULT_PMBASE 0x0500
#ifndef __ACPI__
#define DEFAULT_RCBA ((u8 *)0xfed1c000)
#else
#define DEFAULT_RCBA 0xfed1c000
#endif
#include <southbridge/intel/common/rcba.h>
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X)
#define CROS_GPIO_DEVICE_NAME "CougarPoint"
@ -270,17 +266,6 @@ int rtc_failure(void);
/* Root Complex Register Block */
#define RCBA 0xf0
#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
#define RCBA_AND_OR(bits, x, and, or) \
RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
#define VCH 0x0000 /* 32bit */
#define VCAP1 0x0004 /* 32bit */
#define VCAP2 0x0008 /* 32bit */

41
src/southbridge/intel/common/rcba.h Normal file
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@ -0,0 +1,41 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H
#define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H
#ifndef __ACPI__
#define DEFAULT_RCBA ((u8 *)0xfed1c000)
#else
#define DEFAULT_RCBA 0xfed1c000
#endif
#ifndef __ACPI__
#define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + x)))
#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + x)))
#define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + x)))
#define RCBA_AND_OR(bits, x, and, or) \
(RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)))
#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
#endif /* __ACPI__ */
#endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */

17
src/southbridge/intel/ibexpeak/pch.h
View File

@ -46,11 +46,7 @@
#define DEFAULT_GPIOBASE 0x0480
#define DEFAULT_PMBASE 0x0500
#ifndef __ACPI__
#define DEFAULT_RCBA ((u8 *)0xfed1c000)
#else
#define DEFAULT_RCBA 0xfed1c000
#endif
#include <southbridge/intel/common/rcba.h>
#ifndef __ACPI__
#define DEBUG_PERIODIC_SMIS 0
@ -242,17 +238,6 @@ void southbridge_configure_default_intmap(void);
/* Root Complex Register Block */
#define RCBA 0xf0
#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
#define RCBA_AND_OR(bits, x, and, or) \
RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
#define VCH 0x0000 /* 32bit */
#define VCAP1 0x0004 /* 32bit */
#define VCAP2 0x0008 /* 32bit */