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google/lars: Disable eMMC HS400 capability 

BUG=chrome-os-partner:48017
BRANCH=none
TEST=Verify eMMC is working fine.

Change-Id: If02d969029a9eb8d05148ee958fd34225c8a88fe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dca385c2bbf11c9eb79fd0761b2b335f8fdff491
Original-Change-Id: I371036426f17530409b46af285b18f4522739ee7
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313912
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12618
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
david 2015-11-24 14:41:35 +08:00 committed by Patrick Georgi
parent da1a70ea03
commit 1f35fdde71
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/lars/devicetree.cb
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@ -35,7 +35,7 @@ chip soc/intel/skylake
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "2"
register "IshEnable" = "0"
register "PttSwitch" = "0"