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intel/apollolake: Correct the offsets in gnvs 

Offsets start from 0 instead of 1. Fix this in the gnvs definitions.

BUG=chrome-os-partner:54342

Change-Id: Id6766a8766ef430d19ffcb801bfab43d38de37db
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15180
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Furquan Shaikh 2016-06-14 09:35:04 -07:00
parent d01f5a01e6
commit 1f40ae2d74
2 changed files with 12 additions and 12 deletions
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12
src/soc/intel/apollolake/acpi/globalnvs.asl
View File

@ -28,12 +28,12 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
Offset (0x00),
PCNT, 8, // 0x01 - Processor Count
PPCM, 8, // 0x02 - Max PPC State
LIDS, 8, // 0x03 - LID State
PWRS, 8, // 0x04 - AC Power State
DPTE, 8, // 0x05 - Enable DPTF
CBMC, 32, // 0x06 - 0x09 - Coreboot Memory Console
PCNT, 8, // 0x00 - Processor Count
PPCM, 8, // 0x01 - Max PPC State
LIDS, 8, // 0x02 - LID State
PWRS, 8, // 0x03 - AC Power State
DPTE, 8, // 0x04 - Enable DPTF
CBMC, 32, // 0x05 - 0x08 - Coreboot Memory Console
/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
Offset (0x100),

12
src/soc/intel/apollolake/include/soc/nvs.h
View File

@ -28,12 +28,12 @@
struct global_nvs_t {
/* Miscellaneous */
uint8_t pcnt; /* 0x01 - Processor Count */
uint8_t ppcm; /* 0x02 - Max PPC State */
uint8_t lids; /* 0x03 - LID State */
uint8_t pwrs; /* 0x04 - AC Power State */
uint8_t dpte; /* 0x05 - Enable DPTF */
uint32_t cbmc; /* 0x06 - 0x09 - Coreboot Memory Console */
uint8_t pcnt; /* 0x00 - Processor Count */
uint8_t ppcm; /* 0x01 - Max PPC State */
uint8_t lids; /* 0x02 - LID State */
uint8_t pwrs; /* 0x03 - AC Power State */
uint8_t dpte; /* 0x04 - Enable DPTF */
uint32_t cbmc; /* 0x05 - 0x08 - Coreboot Memory Console */
uint8_t unused[247];
/* ChromeOS specific (0x100 - 0xfff) */