intel/apollolake: Correct the offsets in gnvs
Offsets start from 0 instead of 1. Fix this in the gnvs definitions. BUG=chrome-os-partner:54342 Change-Id: Id6766a8766ef430d19ffcb801bfab43d38de37db Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15180 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
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@ -28,12 +28,12 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
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{
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{
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/* Miscellaneous */
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/* Miscellaneous */
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Offset (0x00),
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Offset (0x00),
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PCNT, 8, // 0x01 - Processor Count
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PCNT, 8, // 0x00 - Processor Count
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PPCM, 8, // 0x02 - Max PPC State
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PPCM, 8, // 0x01 - Max PPC State
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LIDS, 8, // 0x03 - LID State
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LIDS, 8, // 0x02 - LID State
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PWRS, 8, // 0x04 - AC Power State
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PWRS, 8, // 0x03 - AC Power State
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DPTE, 8, // 0x05 - Enable DPTF
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DPTE, 8, // 0x04 - Enable DPTF
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CBMC, 32, // 0x06 - 0x09 - Coreboot Memory Console
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CBMC, 32, // 0x05 - 0x08 - Coreboot Memory Console
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/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
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/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
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Offset (0x100),
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Offset (0x100),
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@ -28,12 +28,12 @@
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struct global_nvs_t {
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struct global_nvs_t {
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/* Miscellaneous */
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/* Miscellaneous */
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uint8_t pcnt; /* 0x01 - Processor Count */
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uint8_t pcnt; /* 0x00 - Processor Count */
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uint8_t ppcm; /* 0x02 - Max PPC State */
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uint8_t ppcm; /* 0x01 - Max PPC State */
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uint8_t lids; /* 0x03 - LID State */
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uint8_t lids; /* 0x02 - LID State */
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uint8_t pwrs; /* 0x04 - AC Power State */
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uint8_t pwrs; /* 0x03 - AC Power State */
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uint8_t dpte; /* 0x05 - Enable DPTF */
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uint8_t dpte; /* 0x04 - Enable DPTF */
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uint32_t cbmc; /* 0x06 - 0x09 - Coreboot Memory Console */
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uint32_t cbmc; /* 0x05 - 0x08 - Coreboot Memory Console */
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uint8_t unused[247];
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uint8_t unused[247];
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/* ChromeOS specific (0x100 - 0xfff) */
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/* ChromeOS specific (0x100 - 0xfff) */
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