soc/intel/skylake: Set proper defaults in chipset devicetree
LPC, P2SB and Power Management controller are always needed. Thus, enable them by default. Change-Id: I20b8cbe536da70fccc3d11e1eedf4a5e14bfc862 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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@ -59,9 +59,9 @@ chip soc/intel/skylake
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device pci 1e.4 alias emmc off end # EMMC
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device pci 1e.4 alias emmc off end # EMMC
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device pci 1e.5 alias sdio off end # SDIO
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device pci 1e.5 alias sdio off end # SDIO
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device pci 1e.6 alias sdxc off end # SDXC
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device pci 1e.6 alias sdxc off end # SDXC
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device pci 1f.0 alias lpc_espi off end # LPC Interface
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device pci 1f.0 alias lpc_espi on end # LPC Interface
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device pci 1f.1 alias p2sb off end # P2SB
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device pci 1f.1 alias p2sb on end # P2SB
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device pci 1f.2 alias pmc off end # Power Management Controller
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device pci 1f.2 alias pmc on end # Power Management Controller
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device pci 1f.3 alias hda off end # Intel HDA
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device pci 1f.3 alias hda off end # Intel HDA
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device pci 1f.4 alias smbus off end # SMBus
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device pci 1f.4 alias smbus off end # SMBus
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device pci 1f.5 alias fast_spi off end # PCH SPI
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device pci 1f.5 alias fast_spi off end # PCH SPI
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