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soc/intel/alderlake: Inform user of memory training

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If memory training is going to happen and early graphics is supported
by the mainboard, an on-screen text message is displayed to inform the
end user.

Memory training can take a while and an impatient end user facing a
black screen for a while may reset the device unnecessarily.

BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=On screen text message during MRC training observed on skolas

Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de0
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70300
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jeremy Compostella 2023-01-04 09:41:52 -07:00 committed by Subrata Banik
parent a439406bdc
commit 1f4d7c772e
2 changed files with 30 additions and 0 deletions
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21
src/soc/intel/alderlake/romstage/fsp_params.c
View file

@ -11,8 +11,10 @@
#include <gpio.h> #include <gpio.h>
#include <intelbasecode/debug_feature.h> #include <intelbasecode/debug_feature.h>
#include <intelblocks/cpulib.h> #include <intelblocks/cpulib.h>
#include <intelblocks/early_graphics.h>
#include <intelblocks/pcie_rp.h> #include <intelblocks/pcie_rp.h>
#include <option.h> #include <option.h>
#include <pc80/vga.h>
#include <soc/iomap.h> #include <soc/iomap.h>
#include <soc/msr.h> #include <soc/msr.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
@ -361,6 +363,16 @@ static void fill_fspm_ibecc_params(FSP_M_CONFIG *m_cfg,
} }
} }
static void inform_user_of_memory_training(void)
{
if (!CONFIG(MAINBOARD_HAS_EARLY_LIBGFXINIT) ||
!early_graphics_init())
return;
vga_write_text(VGA_TEXT_CENTER, VGA_TEXT_HORIZONTAL_MIDDLE,
"Your device is finishing an update. This may take 1-2 minutes.\nPlease do not turn off your device.");
}
static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
const struct soc_intel_alderlake_config *config) const struct soc_intel_alderlake_config *config)
{ {
@ -415,6 +427,15 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
m_cfg->SerialDebugMrcLevel = 0; m_cfg->SerialDebugMrcLevel = 0;
} }
} }
/*
* If valid MRC cache data is not found, FSP should perform a memory
* training. Memory training can take a while so let's inform the end
* user with an on-screen text message.
*/
if (!arch_upd->NvsBufferPtr)
inform_user_of_memory_training();
config = config_of_soc(); config = config_of_soc();
soc_memory_init_params(m_cfg, config); soc_memory_init_params(m_cfg, config);

9
src/soc/intel/alderlake/romstage/romstage.c
View file

@ -6,6 +6,7 @@
#include <fsp/util.h> #include <fsp/util.h>
#include <intelblocks/cfg.h> #include <intelblocks/cfg.h>
#include <intelblocks/cse.h> #include <intelblocks/cse.h>
#include <intelblocks/early_graphics.h>
#include <intelblocks/pmclib.h> #include <intelblocks/pmclib.h>
#include <intelblocks/smbus.h> #include <intelblocks/smbus.h>
#include <intelblocks/thermal.h> #include <intelblocks/thermal.h>
@ -172,4 +173,12 @@ void mainboard_romstage_entry(void)
pmc_set_disb(); pmc_set_disb();
if (!s3wake) if (!s3wake)
save_dimm_info(); save_dimm_info();
/*
* Turn-off early graphics configuration with two purposes:
* - Clear any potentially still on-screen message
* - Allow PEIM graphics driver to smoothly execute in ramstage if
* RUN_FSP_GOP is selected
*/
early_graphics_stop();
} }