mb/google/hatch: Create palkia variant
Add Palkia as a variant of Hatch. BUG=b:150254194 BRANCH=none TEST=none Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I6a303d9fc2be9ea358ad66cd648738187c974193 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38860 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kane Chen
Patrick Georgi
parent
aeaeeb7687
commit
1f4f0b47f5
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@ -99,6 +99,7 @@ config MAINBOARD_PART_NUMBER
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default "Kindred" if BOARD_GOOGLE_KINDRED
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default "Kohaku" if BOARD_GOOGLE_KOHAKU
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default "Mushu" if BOARD_GOOGLE_MUSHU
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default "Palkia" if BOARD_GOOGLE_PALKIA
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default "Nightfury" if BOARD_GOOGLE_NIGHTFURY
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default "Puff" if BOARD_GOOGLE_PUFF
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default "Stryke" if BOARD_GOOGLE_STRYKE
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@ -123,6 +124,7 @@ config VARIANT_DIR
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default "kindred" if BOARD_GOOGLE_KINDRED
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default "kohaku" if BOARD_GOOGLE_KOHAKU
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default "mushu" if BOARD_GOOGLE_MUSHU
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default "palkia" if BOARD_GOOGLE_PALKIA
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default "nightfury" if BOARD_GOOGLE_NIGHTFURY
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default "puff" if BOARD_GOOGLE_PUFF
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default "stryke" if BOARD_GOOGLE_STRYKE
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@ -44,6 +44,13 @@ config BOARD_GOOGLE_MUSHU
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select BOARD_GOOGLE_BASEBOARD_HATCH
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select BOARD_ROMSIZE_KB_16384
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config BOARD_GOOGLE_PALKIA
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bool "-> Palkia"
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select BOARD_GOOGLE_BASEBOARD_HATCH
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select BOARD_ROMSIZE_KB_16384
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select CHROMEOS_DSM_CALIB
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select DRIVERS_I2C_RT1011
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config BOARD_GOOGLE_NIGHTFURY
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bool "-> Nightfury"
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select BOARD_GOOGLE_BASEBOARD_HATCH
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@ -0,0 +1,15 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright 2020 The coreboot project Palkia.
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##
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## SPDX-License-Identifier: GPL-2.0-or-later
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##
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SPD_SOURCES = LP_8G_2133 # 0b0000
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SPD_SOURCES += LP_16G_2133 # 0b0001
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romstage-y += memory.c
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bootblock-y += gpio.c
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ramstage-y += gpio.c
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@ -0,0 +1,141 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2020 The coreboot project Palkia.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include <arch/acpi.h>
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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static const struct pad_config gpio_table[] = {
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/* A8 : PEN_GARAGE_DET_L (wake) */
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PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE),
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/* A10 : FPMCU_PCH_BOOT1 */
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PAD_CFG_GPO(GPP_A10, 0, DEEP),
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/* A18 : ISH_GP0 ==> NC */
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PAD_NC(GPP_A18, NONE),
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/* A19 : ISH_GP1 ==> NC */
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PAD_NC(GPP_A19, NONE),
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/* A20 : ISH_GP2 ==> NC */
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PAD_NC(GPP_A20, NONE),
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/* A22 : ISH_GP4 ==> NC */
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PAD_NC(GPP_A22, NONE),
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/* A23 : ISH_GP5 ==> NC */
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PAD_NC(GPP_A23, NONE),
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/* B19 : GSPI1_CS0# ==> NC */
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PAD_NC(GPP_B19, NONE),
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/* B20 : GSPI1_CLK ==> NC */
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PAD_NC(GPP_B20, NONE),
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/* B21 : GSPI1_MISO ==> NC */
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PAD_NC(GPP_B21, NONE),
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/* B22 : GSPI1_MOSI ==> NC */
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PAD_NC(GPP_B22, NONE),
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/* C1 : SMBDATA ==> NC */
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PAD_NC(GPP_C1, NONE),
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/* C4 : TOUCHSCREEN_DIS_L */
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PAD_CFG_GPO(GPP_C4, 0, DEEP),
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/* C7 : GPP_C7 ==> Touchscreen_INT_L */
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PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, INVERT),
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/* C11 : UART0_CTS# ==> NC */
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PAD_NC(GPP_C11, NONE),
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/* C23 : UART2_CTS# ==> NC */
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PAD_NC(GPP_C23, NONE),
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/* D16 : USI_INT_L */
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PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT),
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/* F0 : GPP_F0 ==> NC */
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PAD_NC(GPP_F0, NONE),
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/* F1 : GPP_F1 ==> NC */
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PAD_NC(GPP_F1, NONE),
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/* F3 : GPP_F3 ==> MEM_STRAP_3 */
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PAD_CFG_GPI(GPP_F3, NONE, PLTRST),
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/* F10 : GPP_F10 ==> MEM_STRAP_2 */
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PAD_CFG_GPI(GPP_F10, NONE, PLTRST),
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/* F11 : EMMC_CMD ==> NC */
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PAD_NC(GPP_F11, NONE),
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/* F20 : EMMC_RCLK ==> NC */
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PAD_NC(GPP_F20, NONE),
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/* F21 : EMMC_CLK ==> NC */
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PAD_NC(GPP_F21, NONE),
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/* F22 : EMMC_RESET# ==> NC */
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PAD_NC(GPP_F22, NONE),
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/* G0 : GPP_G0 ==> NC */
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PAD_NC(GPP_G0, NONE),
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/* G1 : GPP_G1 ==> NC */
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PAD_NC(GPP_G1, NONE),
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/* G2 : GPP_G2 ==> NC */
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PAD_NC(GPP_G2, NONE),
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/* G3 : GPP_G3 ==> NC */
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PAD_NC(GPP_G3, NONE),
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/* G4 : GPP_G4 ==> NC */
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PAD_NC(GPP_G4, NONE),
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/* G5 : GPP_G5 ==> NC */
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PAD_NC(GPP_G5, NONE),
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/* G6 : GPP_G6 ==> NC */
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PAD_NC(GPP_G6, NONE),
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/* H3 : SPKR_PA_EN */
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PAD_CFG_GPO(GPP_H3, 1, DEEP),
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/* H4 : Touchscreen I2C2_SDA */
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PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
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/* H5 : Touchscreen I2C2_SCL */
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PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
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/* H13 : M2_SKT2_CFG1 ==> SPKR_RST_L */
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PAD_CFG_GPO(GPP_H13, 1, DEEP),
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/* H14 : M2_SKT2_CFG2 ==> TOUCHSCREEN_STOP_L */
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PAD_CFG_GPO(GPP_H14, 1, PLTRST),
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/* H19 : TIMESYNC[0] ==> MEM_STRAP_0 */
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PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
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/* H22 : MEM_STRAP_1 */
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PAD_CFG_GPI(GPP_H22, NONE, PLTRST),
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};
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const struct pad_config *override_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(gpio_table);
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return gpio_table;
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}
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/*
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* GPIOs configured before ramstage
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* Note: the Hatch platform's romstage will configure
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* the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins
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* as inputs before it reads them, so they are not
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* needed in this table.
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*/
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static const struct pad_config early_gpio_table[] = {
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/* B15 : H1_SLAVE_SPI_CS_L */
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PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
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/* B16 : H1_SLAVE_SPI_CLK */
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
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/* B17 : H1_SLAVE_SPI_MISO_R */
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : H1_SLAVE_SPI_MOSI_R */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* C14 : BT_DISABLE_L */
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PAD_CFG_GPO(GPP_C14, 0, DEEP),
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/* PCH_WP_OD */
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PAD_CFG_GPI(GPP_C20, NONE, DEEP),
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/* C21 : H1_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
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/* E1 : M2_SSD_PEDET */
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PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
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/* E5 : SATA_DEVSLP1 */
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PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
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/* F2 : MEM_CH_SEL */
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PAD_CFG_GPI(GPP_F2, NONE, PLTRST),
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};
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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@ -0,0 +1,121 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2020 The coreboot project Palkia.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#define DPTF_CPU_PASSIVE 0
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#define DPTF_CPU_CRITICAL 105
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#define DPTF_TSR0_SENSOR_ID 0
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#define DPTF_TSR0_SENSOR_NAME "Battery Charger"
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#define DPTF_TSR0_PASSIVE 59
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#define DPTF_TSR0_CRITICAL 80
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#define DPTF_TSR1_SENSOR_ID 1
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#define DPTF_TSR1_SENSOR_NAME "5V Regulator"
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#define DPTF_TSR1_PASSIVE 0
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#define DPTF_TSR1_CRITICAL 70
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#define DPTF_TSR1_ACTIVE_AC0 42
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#define DPTF_TSR1_ACTIVE_AC1 41
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#define DPTF_TSR1_ACTIVE_AC2 39
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#define DPTF_TSR2_SENSOR_ID 2
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#define DPTF_TSR2_SENSOR_NAME "Ambient"
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#define DPTF_TSR2_PASSIVE 0
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#define DPTF_TSR2_CRITICAL 65
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#define DPTF_TSR3_SENSOR_ID 3
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#define DPTF_TSR3_SENSOR_NAME "CPU"
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#define DPTF_TSR3_PASSIVE 44
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#define DPTF_TSR3_CRITICAL 90
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#define DPTF_ENABLE_CHARGER
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#define DPTF_ENABLE_FAN_CONTROL
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/* Charger performance states, board-specific values from charger and EC */
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Name (CHPS, Package () {
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Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
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Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
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Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
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})
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/* DFPS: Fan Performance States */
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Name (DFPS, Package () {
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0, // Revision
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/*
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* TODO : Need to update this Table after characterization.
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* These are initial reference values.
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*/
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/* Control, Trip Point, Speed, NoiseLevel, Power */
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Package () {90, 0xFFFFFFFF, 6700, 220, 2200},
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Package () {80, 0xFFFFFFFF, 5800, 180, 1800},
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Package () {70, 0xFFFFFFFF, 5000, 145, 1450},
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Package () {60, 0xFFFFFFFF, 4900, 115, 1150},
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Package () {50, 0xFFFFFFFF, 3838, 90, 900},
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Package () {40, 0xFFFFFFFF, 2904, 55, 550},
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Package () {30, 0xFFFFFFFF, 2337, 30, 300},
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Package () {20, 0xFFFFFFFF, 1608, 15, 150},
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Package () {10, 0xFFFFFFFF, 800, 10, 100},
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Package () {0, 0xFFFFFFFF, 0, 0, 50}
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})
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Name (DART, Package () {
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/* Fan effect on CPU */
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0, // Revision
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Package () {
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/*
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* Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
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* AC7, AC8, AC9
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*/
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\_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 90, 70, 50, 50, 0, 0, 0,
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0, 0, 0
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},
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0
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},
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 70, 50, 0, 0, 0, 0,
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0, 0, 0
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},
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0
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},
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR3, 100, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0
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}
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})
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Name (DTRT, Package () {
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/* CPU Throttle Effect on TSR3 */
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Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR3, 100, 60, 0, 0, 0, 0 },
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/* Charger Throttle Effect on TSR0 */
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Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 },
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})
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Name (MPPC, Package ()
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{
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0x2, /* Revision */
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Package () { /* Power Limit 1 */
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0, /* PowerLimitIndex, 0 for Power Limit 1 */
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10000, /* PowerLimitMinimum */
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15000, /* PowerLimitMaximum */
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28000, /* TimeWindowMinimum */
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28000, /* TimeWindowMaximum */
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200 /* StepSize */
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},
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Package () { /* Power Limit 2 */
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1, /* PowerLimitIndex, 1 for Power Limit 2 */
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64000, /* PowerLimitMinimum */
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64000, /* PowerLimitMaximum */
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28000, /* TimeWindowMinimum */
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28000, /* TimeWindowMaximum */
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1000 /* StepSize */
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}
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})
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@ -0,0 +1,14 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2020 The coreboot project Palkia.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef VARIANT_EC_H
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#define VARIANT_EC_H
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#include <baseboard/ec.h>
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#endif
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@ -0,0 +1,20 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2020 The coreboot project Palkia.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef VARIANT_GPIO_H
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#define VARIANT_GPIO_H
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#include <baseboard/gpio.h>
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/* Memory configuration board straps */
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#define GPIO_MEM_CONFIG_0 GPP_H19
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#define GPIO_MEM_CONFIG_1 GPP_H22
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#define GPIO_MEM_CONFIG_2 GPP_F10
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#define GPIO_MEM_CONFIG_3 GPP_F3
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#endif
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@ -0,0 +1,64 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2020 The coreboot project Palkia.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include <baseboard/variants.h>
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#include <baseboard/gpio.h>
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#include <boardid.h>
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#include <gpio.h>
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#include <soc/cnl_memcfg_init.h>
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#include <string.h>
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#include <variant/gpio.h>
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static const struct cnl_mb_cfg baseboard_memcfg = {
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/*
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* The dqs_map arrays map the SoC pins to the lpddr3 pins
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* for both channels.
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*
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* "The index of the array is CPU byte number, the values are DRAM byte
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* numbers." - doc #573387
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*
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* the index = pin number on SoC
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* the value = pin number on lpddr3 part
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*/
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.dqs_map[DDR_CH0] = {4, 7, 5, 6, 0, 3, 2, 1},
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.dqs_map[DDR_CH1] = {0, 3, 2, 1, 4, 7, 6, 5},
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.dq_map[DDR_CH0] = {
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{0xf0, 0xf},
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{0x0, 0xf},
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{0xf0, 0xf},
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{0xf0, 0x0},
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{0xff, 0x0},
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{0xff, 0x0}
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},
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.dq_map[DDR_CH1] = {
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{0xf, 0xf0},
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{0x0, 0xf0},
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{0xf, 0xf0},
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{0xf, 0x0},
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{0xff, 0x0},
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{0xff, 0x0}
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},
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/* Palkia uses 200, 80.6 and 162 rcomp resistors */
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.rcomp_resistor = {200, 81, 162},
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/* Palkia Rcomp target values */
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.rcomp_targets = {100, 40, 40, 23, 40},
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/* Set CaVref config to 0 for LPDDR3 */
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.vref_ca_config = 0,
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/* Disable Early Command Training */
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.ect = 0,
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};
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void variant_memory_params(struct cnl_mb_cfg *bcfg)
|
||||
{
|
||||
memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg));
|
||||
}
|
||||
|
|
@ -0,0 +1,192 @@
|
|||
chip soc/intel/cannonlake
|
||||
register "tdp_pl1_override" = "15"
|
||||
register "tdp_pl2_override" = "64"
|
||||
|
||||
register "SerialIoDevMode" = "{
|
||||
[PchSerialIoIndexI2C0] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C1] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C2] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexI2C4] = PchSerialIoPci,
|
||||
[PchSerialIoIndexSPI0] = PchSerialIoPci,
|
||||
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
|
||||
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
|
||||
}"
|
||||
|
||||
register "usb2_ports[2]" = "USB2_PORT_LONG(OC_SKIP)" # SD CARD
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD CARD
|
||||
|
||||
# No PCIe WiFi
|
||||
register "PcieRpEnable[13]" = "0"
|
||||
|
||||
# Intel Common SoC Config
|
||||
#+-------------------+---------------------------+
|
||||
#| Field | Value |
|
||||
#+-------------------+---------------------------+
|
||||
#| I2C0 | Trackpad |
|
||||
#| I2C1 | Touchscreen |
|
||||
#| I2C2 | 2nd Touchscreen |
|
||||
#| I2C4 | Audio |
|
||||
#+-------------------+---------------------------+
|
||||
register "common_soc_config" = "{
|
||||
.i2c[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 50,
|
||||
.fall_time_ns = 15,
|
||||
.data_hold_time_ns = 330,
|
||||
},
|
||||
.i2c[1] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 60,
|
||||
.fall_time_ns = 25,
|
||||
},
|
||||
.i2c[2] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 60,
|
||||
.fall_time_ns = 25,
|
||||
},
|
||||
.i2c[4] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 120,
|
||||
.fall_time_ns = 120,
|
||||
},
|
||||
}"
|
||||
|
||||
device domain 0 on
|
||||
device pci 14.0 on
|
||||
chip drivers/usb/acpi
|
||||
device usb 0.0 on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Micro SD Card""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device usb 2.2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Left Type-A Port""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 2)"
|
||||
device usb 2.3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
# No WWAN
|
||||
device usb 2.5 off end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
# No Right Tpype-C port
|
||||
device usb 3.1 off end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Micro SD card""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device usb 3.2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Left Type-A Port 1""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 2)"
|
||||
device usb 3.3 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
# Native SD Card interface unused
|
||||
device pci 14.5 off end
|
||||
|
||||
device pci 15.0 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""ELAN0000""
|
||||
register "desc" = ""ELAN Touchpad""
|
||||
register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)"
|
||||
register "wake" = "GPE0_DW0_21"
|
||||
device i2c 15 on end
|
||||
end
|
||||
end
|
||||
|
||||
device pci 15.1 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ELAN9008""
|
||||
register "generic.desc" = ""ELAN Touchscreen USI""
|
||||
register "generic.irq" =
|
||||
"ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
|
||||
register "generic.probed" = "1"
|
||||
register "generic.enable_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)"
|
||||
register "generic.enable_delay_ms" = "12"
|
||||
register "generic.enable_off_delay_ms" = "10"
|
||||
register "generic.has_power_resource" = "1"
|
||||
register "generic.stop_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
|
||||
register "generic.stop_delay_ms" = "15"
|
||||
register "generic.stop_off_delay_ms" = "5"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 10 on end
|
||||
end
|
||||
end # I2C 1
|
||||
|
||||
device pci 15.2 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ELAN9009""
|
||||
register "generic.desc" = ""ELAN Touchscreen USI""
|
||||
register "generic.irq" =
|
||||
"ACPI_IRQ_EDGE_LOW(GPP_C7_IRQ)"
|
||||
register "generic.probed" = "1"
|
||||
register "generic.enable_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)"
|
||||
register "generic.enable_delay_ms" = "12"
|
||||
register "generic.enable_off_delay_ms" = "10"
|
||||
register "generic.has_power_resource" = "1"
|
||||
register "generic.stop_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
|
||||
register "generic.stop_delay_ms" = "15"
|
||||
register "generic.stop_off_delay_ms" = "5"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 10 on end
|
||||
end
|
||||
end #I2C 2
|
||||
|
||||
# I2C #3 unused
|
||||
device pci 15.3 off end
|
||||
|
||||
device pci 19.0 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""10EC5682""
|
||||
register "name" = ""RT58""
|
||||
register "desc" = ""Realtek RT5682""
|
||||
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
|
||||
register "property_count" = "1"
|
||||
# Set the jd_src to RT5668_JD1 for jack detection
|
||||
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
|
||||
register "property_list[0].name" = ""realtek,jd-src""
|
||||
register "property_list[0].integer" = "1"
|
||||
device i2c 1a on end
|
||||
end
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""10EC1011""
|
||||
register "desc" = ""RT1011 Tweeter Left Speaker Amp""
|
||||
register "uid" = "0"
|
||||
register "name" = ""TL""
|
||||
device i2c 38 on end
|
||||
end
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""10EC1011""
|
||||
register "desc" = ""RT1011 Tweeter Right Speaker Amp""
|
||||
register "uid" = "1"
|
||||
register "name" = ""TR""
|
||||
device i2c 39 on end
|
||||
end
|
||||
end #I2C #4
|
||||
# GSPI #1 unused
|
||||
device pci 1e.3 off end
|
||||
|
||||
device pci 1f.3 on
|
||||
chip drivers/generic/max98357a
|
||||
register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)"
|
||||
register "sdmode_delay" = "5"
|
||||
device generic 0 on end
|
||||
end
|
||||
end # Intel I2S
|
||||
end
|
||||
end
|
||||
Loading…
Reference in New Issue