From 1f52edb093aef9b70ce10172bc8c759cdaa1c2ba Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Wed, 1 Jun 2022 17:17:09 +0800
Subject: [PATCH] mb/google/brya/var/mithrax: Update DPTF parameters for
 Mithrax

Follow thermal table from thermal team.

Chang list:
1. Update TEMP_PCT of Active Policy for TSR1.

BUG=b:230829301
TEST=emerge-brya coreboot

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I2a3fbdbe0dbb00597d5785c90c6e4d6ace54f13c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
---
 .../google/brya/variants/mithrax/overridetree.cb       | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/google/brya/variants/mithrax/overridetree.cb b/src/mainboard/google/brya/variants/mithrax/overridetree.cb
index 06426fa386..2318c2c123 100644
--- a/src/mainboard/google/brya/variants/mithrax/overridetree.cb
+++ b/src/mainboard/google/brya/variants/mithrax/overridetree.cb
@@ -99,11 +99,11 @@ chip soc/intel/alderlake
 						.target = DPTF_TEMP_SENSOR_1,
 						.thresholds = {
 								TEMP_PCT(48, 76),
-								TEMP_PCT(45, 65),
-								TEMP_PCT(42, 53),
-								TEMP_PCT(39, 45),
-								TEMP_PCT(36, 39),
-								TEMP_PCT(33, 34),
+								TEMP_PCT(40, 66),
+								TEMP_PCT(38, 53),
+								TEMP_PCT(36, 43),
+								TEMP_PCT(34, 39),
+								TEMP_PCT(32, 33),
 						}
 					}
 				}"