rambi: add per-sku SPD support
There are currently 4 SKUs: 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz Add each of the 4 spds to the build, and use the proper parameters to MRC to use the in-memory SPD information. BUG=chrome-os-partner:22865 BRANCH=None TEST=Built. Noted 1024 bytes of SPD content. Change-Id: Ife96650f9b0032b6bd0d1bdd63b8970e29868365 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172280 Reviewed-on: http://review.coreboot.org/4872 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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5f8ad56358
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@ -32,4 +32,8 @@ config HAVE_ME_BIN
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bool
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bool
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default n
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default n
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config SPD_CBFS_ADDRESS
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hex "Location of SPD in CBFS"
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default 0xfffec000
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endif # BOARD_INTEL_BAYLEYBAY
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endif # BOARD_INTEL_BAYLEYBAY
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@ -17,6 +17,8 @@
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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##
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subdirs-y += spd
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_CHROMEOS) += gpio.c
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ramstage-$(CONFIG_CHROMEOS) += gpio.c
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@ -19,19 +19,60 @@
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#include <stdint.h>
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#include <stdint.h>
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#include <string.h>
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#include <string.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <baytrail/gpio.h>
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#include <baytrail/mrc_wrapper.h>
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#include <baytrail/mrc_wrapper.h>
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#include <baytrail/romstage.h>
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#include <baytrail/romstage.h>
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/*
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* RAM_ID[2:0] are on GPIO_SSUS[39:37]
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* 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
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* 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
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* 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
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* 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz
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*/
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#define SPD_SIZE 256
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#define GPIO_SSUS_37_PAD 57
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#define GPIO_SSUS_38_PAD 50
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#define GPIO_SSUS_39_PAD 58
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static void *get_spd_pointer(char *spd_file_content, int total_spds)
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{
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int ram_id = 0;
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ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0);
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ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1);
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ram_id |= (ssus_get_gpio(GPIO_SSUS_39_PAD) << 2);
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if (ram_id >= total_spds)
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return NULL;
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return &spd_file_content[SPD_SIZE * ram_id];
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}
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void mainboard_romstage_entry(struct romstage_params *rp)
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void mainboard_romstage_entry(struct romstage_params *rp)
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{
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{
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struct cbfs_file *spd_file;
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void *spd_content;
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struct mrc_params mp = {
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struct mrc_params mp = {
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.mainboard = {
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.mainboard = {
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.dram_type = DRAM_DDR3L,
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.dram_type = DRAM_DDR3L,
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.dram_info_location = DRAM_INFO_SPD_SMBUS,
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.dram_info_location = DRAM_INFO_SPD_MEM,
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.spd_addrs = { 0xa0, 0xa2 },
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},
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},
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};
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};
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spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin");
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if (!spd_file)
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die("SPD data not found.");
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/* Both channels are always present. */
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spd_content = get_spd_pointer(CBFS_SUBHEADER(spd_file),
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ntohl(spd_file->len) / SPD_SIZE);
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mp.mainboard.dram_data[0] = spd_content;
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mp.mainboard.dram_data[1] = spd_content;
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rp->mrc_params = ∓
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rp->mrc_params = ∓
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romstage_common(rp);
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romstage_common(rp);
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}
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}
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@ -0,0 +1,46 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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SPD_BIN = $(obj)/spd.bin
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# Order matters for SPD sources. The following indicies
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# define the SPD data to use.
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# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
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# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
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# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
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# 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz
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SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125
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SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
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SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125
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SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA
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SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
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# Include spd rom data
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$(SPD_BIN): $(SPD_DEPS)
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for f in $+; \
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do for c in $$(cat $$f | grep -v ^#); \
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do echo -e -n "\\x$$c"; \
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done; \
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done > $@
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cbfs-files-y += spd.bin
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spd.bin-file := $(SPD_BIN)
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spd.bin-type := 0xab
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spd.bin-position := $(CONFIG_SPD_CBFS_ADDRESS)
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@ -0,0 +1,32 @@
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92 12 0b 03 03 11 02 02
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03 52 01 08 0a 00 fe 00
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69 78 69 3c 69 11 18 81
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00 05 3c 3c 01 40 83 01
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 0f 11 22 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 80 ad 01
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00 00 00 00 00 00 41 5f
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48 4d 54 33 31 32 53 36
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44 46 52 36 41 2d 50 42
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20 20 4e 30 80 ad 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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@ -0,0 +1,32 @@
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92 12 0b 03 04 19 02 02
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03 52 01 08 0a 00 fe 00
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69 78 69 3c 69 11 18 81
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20 08 3c 3c 01 40 83 01
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 0f 11 62 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 80 ad 01
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00 00 00 00 00 00 ff ab
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48 4d 54 34 32 35 53 36
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41 46 52 36 41 2d 50 42
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20 20 4e 30 80 ad 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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@ -0,0 +1,32 @@
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92 11 0b 03 03 11 02 02
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03 11 01 08 0a 00 fe 00
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69 78 69 3c 69 11 18 86
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50 00 3c 3c 01 40 83 05
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 0f 01 02 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 80 2c 00
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00 00 00 00 00 00 6a 15
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34 4b 54 46 32 35 36 36
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34 48 5a 2d 31 47 36 45
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31 20 45 31 80 2c 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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@ -0,0 +1,32 @@
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92 11 0b 03 04 19 02 02
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03 11 01 08 0a 00 fe 00
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69 78 69 3c 69 11 18 86
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20 08 3c 3c 01 40 83 05
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 0f 01 02 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 80 2c 00
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00 00 00 00 00 00 19 d2
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34 4b 54 46 32 35 36 36
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34 48 5a 2d 31 47 36 45
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31 20 45 31 80 2c 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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ff ff ff ff ff ff ff ff
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