- Fix UDELAY options and HAVE_INIT_TIMER [kconfig]
(defaults to UDELAY_IO again, like newconfig) - Use UDELAY_TSC on Via C7 [kconfig] - Support Tinybootblock on Intel CPUs - set XIP location correctly for Tinybootblock on Intel - provide correct XIP location in Tinybootblock configuration - Make kontron/986lcd-m use Tinybootblock - Some kconfig fixes to kontron/986lcd-m [kconfig] Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi
parent
ce56835a5c
commit
1f807fd42f
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@ -186,6 +186,7 @@ config HAVE_HARD_RESET
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config HAVE_INIT_TIMER
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bool
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default n if UDELAY_IO
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default y
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config HAVE_MAINBOARD_RESOURCES
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@ -67,13 +67,13 @@ $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootbl
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# Build the romstage
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$(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $(initobjs) $(obj)/romstage/ldscript.ld
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@printf " LINK $(subst $(obj)/,,$(@))\n"
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printf "CONFIG_ROMBASE = 0x0;\n" > $(obj)/location.ld
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printf "CONFIG_ROMBASE = 0x0;\nAUTO_XIP_ROM_BASE = 0x0;\n" > $(obj)/location.ld
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$(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(initobjs)
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$(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin
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printf "CONFIG_ROMBASE = 0x" > $(obj)/location.ld
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$(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin fallback/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt
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cat $(obj)/location.txt >> $(obj)/location.ld
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printf ";\n" >> $(obj)/location.ld
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printf ';\nAUTO_XIP_ROM_BASE = CONFIG_ROMBASE & ~(CONFIG_XIP_ROM_SIZE - 1);\n' >> $(obj)/location.ld
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$(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(initobjs)
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$(NM) -n $(obj)/romstage.elf | sort > $(obj)/romstage.map
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$(OBJCOPY) -O binary $(obj)/romstage.elf $@
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@ -114,7 +114,13 @@ clear_mtrrs:
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/* Enable cache for our code in Flash because we do XIP here */
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movl $MTRRphysBase_MSR(1), %ecx
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xorl %edx, %edx
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movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
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#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
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#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
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#else
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#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
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#endif
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movl $REAL_XIP_ROM_BASE, %eax
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orl $MTRR_TYPE_WRBACK, %eax
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wrmsr
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movl $MTRRphysMask_MSR(1), %ecx
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@ -25,6 +25,7 @@ void stage1_main(unsigned long bist)
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{
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unsigned int cpu_reset = 0;
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#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
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#if CONFIG_USE_FALLBACK_IMAGE == 1
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/* Is this a deliberate reset by the bios */
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if (bios_reset_detected() && last_boot_normal()) {
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@ -45,6 +46,7 @@ void stage1_main(unsigned long bist)
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: "a" (bist) /* inputs */
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);
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fallback_image:
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#endif
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#endif
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real_main(bist);
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@ -104,7 +104,13 @@ clear_mtrrs:
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/* Enable cache for our code in Flash because we do XIP here */
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movl $MTRRphysBase_MSR(1), %ecx
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xorl %edx, %edx
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movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
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#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
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#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
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#else
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#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
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#endif
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movl $REAL_XIP_ROM_BASE, %eax
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orl $MTRR_TYPE_WRBACK, %eax
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wrmsr
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movl $MTRRphysMask_MSR(1), %ecx
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@ -27,6 +27,7 @@ void stage1_main(unsigned long bist)
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{
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unsigned int cpu_reset = 0;
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#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
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#if CONFIG_USE_FALLBACK_IMAGE == 1
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/* Is this a deliberate reset by the bios */
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if (bios_reset_detected() && last_boot_normal()) {
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@ -47,6 +48,7 @@ void stage1_main(unsigned long bist)
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: "a" (bist) /* inputs */
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);
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fallback_image:
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#endif
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#endif
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real_main(bist);
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@ -111,7 +111,13 @@ clear_mtrrs:
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/* Enable cache for our code in Flash because we do XIP here */
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movl $MTRRphysBase_MSR(1), %ecx
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xorl %edx, %edx
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movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
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#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
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#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
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#else
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#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
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#endif
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movl $REAL_XIP_ROM_BASE, %eax
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orl $MTRR_TYPE_WRBACK, %eax
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wrmsr
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movl $MTRRphysMask_MSR(1), %ecx
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@ -27,6 +27,7 @@ void stage1_main(unsigned long bist)
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{
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unsigned int cpu_reset = 0;
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#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
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#if CONFIG_USE_FALLBACK_IMAGE == 1
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/* Is this a deliberate reset by the bios */
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if (bios_reset_detected() && last_boot_normal()) {
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@ -47,6 +48,7 @@ void stage1_main(unsigned long bist)
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: "a" (bist) /* inputs */
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);
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fallback_image:
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#endif
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#endif
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real_main(bist);
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@ -1,2 +1,3 @@
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config CPU_VIA_C7
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bool
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select UDELAY_TSC
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@ -8,6 +8,7 @@ config WAIT_BEFORE_CPUS_INIT
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config UDELAY_IO
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bool
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default y if !UDELAY_LAPIC && !UDELAY_TSC
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default n
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config UDELAY_LAPIC
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@ -21,7 +21,7 @@ config BOARD_KONTRON_986LCD_M
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select IOAPIC
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select USE_DCACHE_RAM
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select GFXUMA
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select HAVE_MOVNTI
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select TINY_BOOTBLOCK
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config MAINBOARD_DIR
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string
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@ -72,8 +72,3 @@ config FALLBACK_VGA_BIOS_FILE
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string
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default "amipci_01.20"
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depends on BOARD_KONTRON_986LCD_M
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config HAVE_ACPI_SLIC
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bool
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default n
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depends on BOARD_KONTRON_986LCD_M
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@ -40,18 +40,12 @@ smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o
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initobj-y += crt0.o
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# FIXME in $(top)/Makefile
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crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
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crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
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crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
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crt0-y += ../../../../src/arch/i386/lib/id.inc
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crt0-y += ../../../../src/cpu/intel/model_6ex/cache_as_ram.inc
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crt0-y += auto.inc
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ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
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ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
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ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
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ldscript-y += ../../../../src/arch/i386/lib/id.lds
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ldscript-y += ../../../../src/arch/i386/lib/failover.lds
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ldscript-y += ../../../../src/cpu/x86/32bit/entry32.lds
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ifdef POST_EVALUATION
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