From 1f83ffac1b30e7b6ed59fb26ee2ba57cec4938eb Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Tue, 21 Jun 2016 19:07:32 -0700 Subject: [PATCH] gru: include ram_code in coreboot table This is needed to ensure that the ram-code node is included in the device tree by depthcharge. BRANCH=none BUG=chrome-os-partner:54566 TEST=built updated firmware, booted on kevin into Linux shell, checked the device tree contents: localhost ~ # od -tx1 /proc/device-tree/firmware/coreboot/ram-code 0000000 00 00 00 01 0000004 localhost # Change-Id: Ibe96e3bc8fc0106013241738f5726783d74bd78b Signed-off-by: Martin Roth Original-Commit-Id: 53c002114f7044b88728c9e17150cd3a2cf1f80f Original-Change-Id: Iba573fba9f9b88b87867c6963e48215e254319ed Original-Signed-off-by: Vadim Bendebury Original-Reviewed-on: https://chromium-review.googlesource.com/354705 Original-Reviewed-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/15566 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/gru/Kconfig | 1 + src/mainboard/google/gru/Makefile.inc | 1 + src/mainboard/google/gru/boardid.c | 5 ----- src/mainboard/google/gru/sdram_configs.c | 24 +++++++++++++++++------- 4 files changed, 19 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index 170e358bda..1b42059032 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_NATIVE_VGA_INIT + select RAM_CODE_SUPPORT select RTC select SOC_ROCKCHIP_RK3399 select SPI_FLASH diff --git a/src/mainboard/google/gru/Makefile.inc b/src/mainboard/google/gru/Makefile.inc index a209d1bdf3..9e87fadd1c 100644 --- a/src/mainboard/google/gru/Makefile.inc +++ b/src/mainboard/google/gru/Makefile.inc @@ -33,3 +33,4 @@ ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c +ramstage-y += sdram_configs.c # Needed for ram_code() diff --git a/src/mainboard/google/gru/boardid.c b/src/mainboard/google/gru/boardid.c index 1d37a867a8..b0c1eaf17e 100644 --- a/src/mainboard/google/gru/boardid.c +++ b/src/mainboard/google/gru/boardid.c @@ -59,8 +59,3 @@ uint8_t board_id(void) adc_reading); return 0; } - -uint32_t ram_code(void) -{ - return 0; -} diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index 92e00efdba..f1f889c334 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -38,19 +38,29 @@ enum dram_speeds { /* dram_928MHz = 4, */ }; +static enum dram_speeds get_sdram_index(void) +{ + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) + return dram_300MHz; + else if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU)) + return dram_800MHz; + else + return dram_200MHz; +} + const struct rk3399_sdram_params *get_sdram_config() { - enum dram_speeds speed; - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) - speed = dram_300MHz; - else if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU)) - speed = dram_800MHz; - else - speed = dram_200MHz; + enum dram_speeds speed = get_sdram_index(); printk(BIOS_INFO, "Using SDRAM configuration for %d MHz\n", sdram_configs[speed].ddr_freq / (1000 * 1000)); return &sdram_configs[speed]; } + + +uint32_t ram_code(void) +{ + return get_sdram_index(); +}