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soc/intel/alderlake: Enable Irms UPD for ADL 

This change sets Irms config in FSP if TdcTimeWindow and TdcCurrentLimit
is set to non zero. It results VR TDC Input current to be treated as it
is root mean square.

This change also optimizes the check of TdcTimeWindow and TdcCurrentLimit
for TdcEnable UPD.

BRANCH=None
TEST=Build and boot brya with debug FSP and verify Irms UPD value
from logs

Change-Id: Ice5c775ef9560503109957a1ed994af1d287aafc
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
This commit is contained in:
Ronak Kanabar 2021-07-15 19:02:22 +05:30 committed by Felix Held
parent 5eb5f863b5
commit 1f88a71aa8
1 changed files with 7 additions and 4 deletions
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9
src/soc/intel/alderlake/vr_config.c
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@ -88,8 +88,6 @@ void fill_vr_domain_config(FSP_S_CONFIG *s_cfg,
s_cfg->IccMax[domain] = cfg->icc_max; s_cfg->IccMax[domain] = cfg->icc_max;
s_cfg->TdcTimeWindow[domain] = cfg->tdc_timewindow; s_cfg->TdcTimeWindow[domain] = cfg->tdc_timewindow;
s_cfg->TdcCurrentLimit[domain] = cfg->tdc_currentlimit; s_cfg->TdcCurrentLimit[domain] = cfg->tdc_currentlimit;
if (cfg->tdc_timewindow != 0 && cfg->tdc_currentlimit != 0)
s_cfg->TdcEnable[domain] = 1;
} else { } else {
uint16_t mch_id = 0; uint16_t mch_id = 0;
@ -110,7 +108,12 @@ void fill_vr_domain_config(FSP_S_CONFIG *s_cfg,
s_cfg->TdcCurrentLimit[domain] = load_table(vr_config_tdc_currentlimit, s_cfg->TdcCurrentLimit[domain] = load_table(vr_config_tdc_currentlimit,
ARRAY_SIZE(vr_config_tdc_currentlimit), ARRAY_SIZE(vr_config_tdc_currentlimit),
domain, mch_id); domain, mch_id);
if (s_cfg->TdcTimeWindow[domain] != 0 && s_cfg->TdcCurrentLimit[domain] != 0) }
/* Check TdcTimeWindow and TdcCurrentLimit,
Set TdcEnable and Set VR TDC Input current to root mean square */
if (s_cfg->TdcTimeWindow[domain] != 0 && s_cfg->TdcCurrentLimit[domain] != 0) {
s_cfg->TdcEnable[domain] = 1; s_cfg->TdcEnable[domain] = 1;
s_cfg->Irms[domain] = 1;
} }
} }