soc/intel/jasperlake: Remove GPIO community 2 from DSDT
The kernel driver enumerates communities 0, 1, 4, and 5, and assigns these addresses based on the BARs enumerated by coreboot. Coreboot was defining communities 0, 1, 2, 4, and 5. This meant the kernel was not controlling GPIOs in communities 4 and 5, since the resources were wrong. Remove community 2 for now. We can add it back if the kernel ends up needing it. BUG=b:169444894 TEST=Test controlling GPP_E5, verify actually toggles register. Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: I823e1aa942cfccadde01b9371d481457ab088c31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46115 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -18,7 +18,6 @@ Device (GPIO)
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{
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{
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Memory32Fixed (ReadWrite, 0, 0, COM0)
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Memory32Fixed (ReadWrite, 0, 0, COM0)
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Memory32Fixed (ReadWrite, 0, 0, COM1)
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Memory32Fixed (ReadWrite, 0, 0, COM1)
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Memory32Fixed (ReadWrite, 0, 0, COM2)
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Memory32Fixed (ReadWrite, 0, 0, COM4)
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Memory32Fixed (ReadWrite, 0, 0, COM4)
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Memory32Fixed (ReadWrite, 0, 0, COM5)
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Memory32Fixed (ReadWrite, 0, 0, COM5)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
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@ -39,12 +38,6 @@ Device (GPIO)
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BAS1 = ^^PCRB (PID_GPIOCOM1)
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BAS1 = ^^PCRB (PID_GPIOCOM1)
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LEN1 = GPIO_BASE_SIZE
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LEN1 = GPIO_BASE_SIZE
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/* GPIO Community 2 */
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CreateDWordField (^RBUF, ^COM2._BAS, BAS2)
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CreateDWordField (^RBUF, ^COM2._LEN, LEN2)
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BAS2 = ^^PCRB (PID_GPIOCOM2)
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LEN2 = GPIO_BASE_SIZE
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/* GPIO Community 4 */
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/* GPIO Community 4 */
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CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
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CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
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CreateDWordField (^RBUF, ^COM4._LEN, LEN4)
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CreateDWordField (^RBUF, ^COM4._LEN, LEN4)
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