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src/superio/ite/it8772f: Separate mainboard from SIO at obj level 

Remove #include early_serial.c and rename to early_init.c as no actual
UART configuration is done here. Note that this SIO component still
hard codes its base address to 0x2e.

Change-Id: Ieef32ac7285246717f0519ffed4314ba28cd47dc
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6271
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Edward O'Callaghan 2014-07-14 16:31:25 +10:00 committed by Patrick Georgi
parent d5339ae0b7
commit 1f9653a1bc
7 changed files with 125 additions and 113 deletions
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4
src/mainboard/google/panther/romstage.c
View File

@ -30,11 +30,11 @@
#include <southbridge/intel/lynxpoint/lp_gpio.h>
#include "gpio.h"
#include "superio/ite/it8772f/it8772f.h"
#include "superio/ite/it8772f/early_serial.c"
#include "superio/ite/common/ite.h"
#define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO)
#define DUMMY_DEV PNP_DEV(0x2e, 0)
const struct rcba_config_instruction rcba_config[] = {
@ -145,7 +145,7 @@ void mainboard_romstage_entry(unsigned long bist)
/* Early SuperIO setup */
ite_kill_watchdog(GPIO_DEV);
it8772f_ac_resume_southbridge();
it8772f_ac_resume_southbridge(DUMMY_DEV);
pch_enable_lpc();
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

17
src/mainboard/samsung/stumpy/romstage.c
View File

@ -34,8 +34,6 @@
#include <bootmode.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8772f/it8772f.h>
/* FIXME: SUPERIO include.c */
#include "superio/ite/it8772f/early_serial.c"
#include "northbridge/intel/sandybridge/sandybridge.h"
#include "northbridge/intel/sandybridge/raminit.h"
#include "southbridge/intel/bd82x6x/pch.h"
@ -61,6 +59,7 @@
#endif
#define USB_RESET_DISABLE_MAGIC (0xdd) /* Disable if set to this */
#define DUMMY_DEV PNP_DEV(0x2e, 0)
#define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO)
@ -148,29 +147,29 @@ static void setup_sio_gpios(void)
* GPIO10 as USBPWRON12#
* GPIO12 as USBPWRON13#
*/
it8772f_gpio_setup(1, 0x05, 0x05, 0x00, 0x05, 0x05);
it8772f_gpio_setup(DUMMY_DEV, 1, 0x05, 0x05, 0x00, 0x05, 0x05);
/*
* GPIO22 as wake SCI#
*/
it8772f_gpio_setup(2, 0x04, 0x04, 0x00, 0x04, 0x04);
it8772f_gpio_setup(DUMMY_DEV, 2, 0x04, 0x04, 0x00, 0x04, 0x04);
/*
* GPIO32 as EXTSMI#
*/
it8772f_gpio_setup(3, 0x04, 0x04, 0x00, 0x04, 0x04);
it8772f_gpio_setup(DUMMY_DEV, 3, 0x04, 0x04, 0x00, 0x04, 0x04);
/*
* GPIO45 as LED_POWER#
*/
it8772f_gpio_setup(4, 0x20, 0x20, 0x20, 0x20, 0x20);
it8772f_gpio_setup(DUMMY_DEV, 4, 0x20, 0x20, 0x20, 0x20, 0x20);
/*
* GPIO51 as USBPWRON8#
* GPIO52 as USBPWRON1#
*/
it8772f_gpio_setup(5, 0x06, 0x06, 0x00, 0x06, 0x06);
it8772f_gpio_setup(6, 0x00, 0x00, 0x00, 0x00, 0x00);
it8772f_gpio_setup(DUMMY_DEV, 5, 0x06, 0x06, 0x00, 0x06, 0x06);
it8772f_gpio_setup(DUMMY_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00);
}
void main(unsigned long bist)
@ -239,7 +238,7 @@ void main(unsigned long bist)
setup_sio_gpios();
/* Early SuperIO setup */
it8772f_ac_resume_southbridge();
it8772f_ac_resume_southbridge(DUMMY_DEV);
ite_kill_watchdog(GPIO_DEV);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();

20
src/mainboard/samsung/stumpy/smihandler.c
View File

@ -26,8 +26,10 @@
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
/* Include romstage serial for SIO helper functions */
#include <superio/ite/it8772f/early_serial.c>
/* FIXME: Include romstage serial for SIO helper functions */
#include <superio/ite/it8772f/early_init.c>
//#include <superio/ite/it8772f/it8772f.h>
#define DUMMY_DEV PNP_DEV(0x2e, 0)
int mainboard_io_trap_handler(int smif)
{
@ -64,18 +66,18 @@ void mainboard_smi_sleep(u8 slp_typ)
case 3:
case 4:
/* Blink LED */
it8772f_enter_conf();
it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
it8772f_enter_conf(DUMMY_DEV);
it8772f_sio_write(DUMMY_DEV, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
/* Enable blink pin map */
it8772f_sio_write(IT8772F_GPIO_LED_BLINK1_PINMAP,
it8772f_sio_write(DUMMY_DEV, IT8772F_GPIO_LED_BLINK1_PINMAP,
SIO_GPIO_BLINK_GPIO45);
/* Enable 4HZ blink */
it8772f_sio_write(IT8772F_GPIO_LED_BLINK1_CONTROL, 0x02);
it8772f_sio_write(DUMMY_DEV, IT8772F_GPIO_LED_BLINK1_CONTROL, 0x02);
/* Set GPIO to alternate function */
reg8 = it8772f_sio_read(GPIO_REG_ENABLE(3));
reg8 = it8772f_sio_read(DUMMY_DEV, GPIO_REG_ENABLE(3));
reg8 &= ~(1 << 5);
it8772f_sio_write(GPIO_REG_ENABLE(3), reg8);
it8772f_exit_conf();
it8772f_sio_write(DUMMY_DEV, GPIO_REG_ENABLE(3), reg8);
it8772f_exit_conf(DUMMY_DEV);
break;
case 5:

1
src/superio/ite/it8772f/Makefile.inc
View File

@ -18,4 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
romstage-$(CONFIG_SUPERIO_ITE_IT8772F) += early_init.c
ramstage-$(CONFIG_SUPERIO_ITE_IT8772F) += superio.c

87
src/superio/ite/it8772f/early_init.c Normal file
View File

@ -0,0 +1,87 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <device/pnp_def.h>
#include "it8772f.h"
/* NOTICE: This file is deprecated, use ite/common instead */
/* RAMstage equiv */
/* u8 pnp_read_config(device_t dev, u8 reg) */
u8 it8772f_sio_read(device_t dev, u8 reg)
{
u16 port = dev >> 8;
outb(reg, port);
return inb(port + 1);
}
/* RAMstage equiv */
/* void pnp_write_config(device_t dev, u8 reg, u8 value) */
void it8772f_sio_write(device_t dev, u8 reg, u8 value)
{
u16 port = dev >> 8;
outb(reg, port);
outb(value, port + 1);
}
void it8772f_enter_conf(device_t dev)
{
u16 port = dev >> 8;
outb(0x87, port);
outb(0x01, port);
outb(0x55, port);
outb((port == 0x4e) ? 0xaa : 0x55, port);
}
void it8772f_exit_conf(device_t dev)
{
it8772f_sio_write(dev, IT8772F_CONFIG_REG_CC, 0x02);
}
/* Set AC resume to be up to the Southbridge */
void it8772f_ac_resume_southbridge(device_t dev)
{
it8772f_enter_conf(dev);
it8772f_sio_write(dev, IT8772F_CONFIG_REG_LDN, IT8772F_EC);
it8772f_sio_write(dev, 0xf4, 0x60);
it8772f_exit_conf(dev);
}
/* Configure a set of GPIOs */
void it8772f_gpio_setup(device_t dev, int set, u8 select, u8 polarity,
u8 pullup, u8 output, u8 enable)
{
set--; /* Set 1 is offset 0 */
it8772f_enter_conf(dev);
it8772f_sio_write(dev, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
if (set < 5) {
it8772f_sio_write(dev, GPIO_REG_SELECT(set), select);
it8772f_sio_write(dev, GPIO_REG_ENABLE(set), enable);
it8772f_sio_write(dev, GPIO_REG_POLARITY(set), polarity);
}
it8772f_sio_write(dev, GPIO_REG_OUTPUT(set), output);
it8772f_sio_write(dev, GPIO_REG_PULLUP(set), pullup);
it8772f_exit_conf(dev);
}

88
src/superio/ite/it8772f/early_serial.c
View File

@ -1,88 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <device/pnp_def.h>
#include "it8772f.h"
/* NOTICE: This file is deprecated, use ite/common instead */
/* The base address is 0x2e or 0x4e, depending on config bytes. */
/* FIXME: SUPERIO include.c */
#define SIO_BASE 0x2e
#define SIO_INDEX SIO_BASE
#define SIO_DATA (SIO_BASE + 1)
/* Global configuration registers. */
#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
#define IT8772F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
u8 it8772f_sio_read(u8 index)
{
outb(index, SIO_BASE);
return inb(SIO_DATA);
}
void it8772f_sio_write(u8 index, u8 value)
{
outb(index, SIO_BASE);
outb(value, SIO_DATA);
}
static void it8772f_enter_conf(void)
{
u16 port = SIO_BASE;
outb(0x87, port);
outb(0x01, port);
outb(0x55, port);
outb((port == 0x4e) ? 0xaa : 0x55, port);
}
static void it8772f_exit_conf(void)
{
it8772f_sio_write(IT8772F_CONFIG_REG_CC, 0x02);
}
/* Set AC resume to be up to the Southbridge */
void it8772f_ac_resume_southbridge(void)
{
it8772f_enter_conf();
it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_EC);
it8772f_sio_write(0xf4, 0x60);
it8772f_exit_conf();
}
/* Configure a set of GPIOs */
void it8772f_gpio_setup(int set, u8 select, u8 polarity, u8 pullup,
u8 output, u8 enable)
{
set--; /* Set 1 is offset 0 */
it8772f_enter_conf();
it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
if (set < 5) {
it8772f_sio_write(GPIO_REG_SELECT(set), select);
it8772f_sio_write(GPIO_REG_ENABLE(set), enable);
it8772f_sio_write(GPIO_REG_POLARITY(set), polarity);
}
it8772f_sio_write(GPIO_REG_OUTPUT(set), output);
it8772f_sio_write(GPIO_REG_PULLUP(set), pullup);
it8772f_exit_conf();
}

21
src/superio/ite/it8772f/it8772f.h
View File

@ -103,10 +103,21 @@
#define GPIO_REG_ENABLE(x) (0xc0 + (x))
#define GPIO_REG_OUTPUT(x) (0xc8 + (x))
u8 it8772f_sio_read(u8 index);
void it8772f_sio_write(u8 index, u8 value);
void it8772f_ac_resume_southbridge(void);
void it8772f_gpio_setup(int set, u8 func_select, u8 polarity, u8 pullup,
u8 output, u8 enable);
#include <arch/io.h>
#include <stdint.h>
u8 it8772f_sio_read(device_t dev, u8 reg);
void it8772f_sio_write(device_t dev, u8 reg, u8 value);
void it8772f_ac_resume_southbridge(device_t dev);
void it8772f_gpio_setup(device_t dev, int set, u8 select, u8 polarity,
u8 pullup, u8 output, u8 enable);
/* FIXME: should be static so will be removed later.. */
/* Global configuration registers. */
#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
#define IT8772F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
void it8772f_enter_conf(device_t dev);
void it8772f_exit_conf(device_t dev);
#endif /* SUPERIO_ITE_IT8772F_H */