diff --git a/src/mainboard/example/Kconfig b/src/mainboard/example/Kconfig new file mode 100644 index 0000000000..5afc8ee5a9 --- /dev/null +++ b/src/mainboard/example/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_EXAMPLE + +choice + prompt "Mainboard model" + +source "src/mainboard/example/*/Kconfig.name" + +endchoice + +source "src/mainboard/example/*/Kconfig" + +config MAINBOARD_VENDOR + default "Example" + +endif # VENDOR_EXAMPLE diff --git a/src/mainboard/example/Kconfig.name b/src/mainboard/example/Kconfig.name new file mode 100644 index 0000000000..9ffc1738bc --- /dev/null +++ b/src/mainboard/example/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_EXAMPLE + bool "Example boards" diff --git a/src/mainboard/example/min86/Kconfig b/src/mainboard/example/min86/Kconfig new file mode 100644 index 0000000000..3a962e27f4 --- /dev/null +++ b/src/mainboard/example/min86/Kconfig @@ -0,0 +1,14 @@ +if BOARD_EXAMPLE_MIN86 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_EXAMPLE_MIN86 + select MISSING_BOARD_RESET + +config MAINBOARD_DIR + default "example/min86" + +config MAINBOARD_PART_NUMBER + default "Min86" + +endif diff --git a/src/mainboard/example/min86/Kconfig.name b/src/mainboard/example/min86/Kconfig.name new file mode 100644 index 0000000000..33131930f5 --- /dev/null +++ b/src/mainboard/example/min86/Kconfig.name @@ -0,0 +1,11 @@ +config BOARD_EXAMPLE_MIN86 + bool "Minimal x86 fake board" + help + This example mainboard code along with the example/min86 SoC + should serve as a minimal example how a buildable x86 SoC code + base can look like. + + This can serve, for instance, as a basis to add new SoCs to + coreboot. Starting with a buildable commit should help with + the review of the actual code, and also avoid any regressions + when common coreboot code changes. diff --git a/src/mainboard/example/min86/board_info.txt b/src/mainboard/example/min86/board_info.txt new file mode 100644 index 0000000000..c778859fab --- /dev/null +++ b/src/mainboard/example/min86/board_info.txt @@ -0,0 +1 @@ +Category: misc diff --git a/src/mainboard/example/min86/devicetree.cb b/src/mainboard/example/min86/devicetree.cb new file mode 100644 index 0000000000..9af04c091a --- /dev/null +++ b/src/mainboard/example/min86/devicetree.cb @@ -0,0 +1,6 @@ +chip soc/example/min86 + + device domain 0 on + end + +end diff --git a/src/soc/example/Kconfig b/src/soc/example/Kconfig new file mode 100644 index 0000000000..5bc004aadb --- /dev/null +++ b/src/soc/example/Kconfig @@ -0,0 +1 @@ +source "src/soc/example/*/Kconfig" diff --git a/src/soc/example/min86/Kconfig b/src/soc/example/min86/Kconfig new file mode 100644 index 0000000000..38b23c0dd2 --- /dev/null +++ b/src/soc/example/min86/Kconfig @@ -0,0 +1,25 @@ +config SOC_EXAMPLE_MIN86 + bool + help + This example SoC code along with the example/min86 mainboard + should serve as a minimal example how a buildable x86 SoC code + base can look like. + + This can serve, for instance, as a basis to add new SoCs to + coreboot. Starting with a buildable commit should help with + the review of the actual code, and also avoid any regressions + when common coreboot code changes. + +if SOC_EXAMPLE_MIN86 + +config SOC_SPECIFIC_OPTIONS + def_bool y + select ARCH_ALL_STAGES_X86_32 + select NO_MONOTONIC_TIMER + select NO_MMCONF_SUPPORT + select UNKNOWN_TSC_RATE + +config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld + default 0x100 + +endif diff --git a/src/soc/example/min86/Makefile.inc b/src/soc/example/min86/Makefile.inc new file mode 100644 index 0000000000..9c1c7f0331 --- /dev/null +++ b/src/soc/example/min86/Makefile.inc @@ -0,0 +1,15 @@ +ifeq ($(CONFIG_SOC_EXAMPLE_MIN86),y) + +bootblock-y += cache_as_ram.S +bootblock-y += ../../../cpu/intel/car/bootblock.c + +postcar-y += exit_car.S + +romstage-y += romstage.c + +ramstage-y += chip.c +ramstage-y += timer.c + +subdirs-y += ../../../cpu/x86/mtrr + +endif diff --git a/src/soc/example/min86/cache_as_ram.S b/src/soc/example/min86/cache_as_ram.S new file mode 100644 index 0000000000..a350143834 --- /dev/null +++ b/src/soc/example/min86/cache_as_ram.S @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +.global bootblock_pre_c_entry + +.code32 +bootblock_pre_c_entry: + call bootblock_c_entry_bist + +.Lhlt: + hlt + jmp .Lhlt diff --git a/src/soc/example/min86/chip.c b/src/soc/example/min86/chip.c new file mode 100644 index 0000000000..dd09891e3c --- /dev/null +++ b/src/soc/example/min86/chip.c @@ -0,0 +1,3 @@ +#include + +struct chip_operations soc_example_min86_ops = { NULL }; diff --git a/src/soc/example/min86/exit_car.S b/src/soc/example/min86/exit_car.S new file mode 100644 index 0000000000..0f1b227c2d --- /dev/null +++ b/src/soc/example/min86/exit_car.S @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +.global chipset_teardown_car + +.code32 +chipset_teardown_car: + /* Return to caller. */ + jmp *%esp diff --git a/src/soc/example/min86/romstage.c b/src/soc/example/min86/romstage.c new file mode 100644 index 0000000000..91074b2012 --- /dev/null +++ b/src/soc/example/min86/romstage.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +asmlinkage void car_stage_entry(void) +{ +} diff --git a/src/soc/example/min86/timer.c b/src/soc/example/min86/timer.c new file mode 100644 index 0000000000..9054ffd972 --- /dev/null +++ b/src/soc/example/min86/timer.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void init_timer(void) +{ +}