armv7/exynos5250: Deprecate sdelay in favor of udelay

This gets rid of the clock-tick based sdelay in favor of udelay().
udelay() is more consistent and easier to work with, and this allows
us to carry one less variation of timers (and headers and sources...).

Every 1 unit in the sdelay() argument was assumed to cause a delay of
2 clock ticks (@1.7GHz). So the conversion factor is roughly:
sdelay(N) = udelay(((N * 2) / 1.7 * 10^9) * 10^6)
          = udelay((N * 2) / (1.7 * 10^3))

The sdelay() periods used were:
sdelay(100) --> udelay(1)
sdelay(0x10000) --> udelay(78) (rounded up to udelay(100))

There was one instance of sdelay(10000), which looked like sort of a
typo since sdelay(0x10000) was used elsewhere. sdelay(10000) should
approximate to about 12us, so we'll stick with that for now and leave
a note.

Change-Id: I5e7407865ceafa701eea1d613bbe50cf4734f33e
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3079
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/arch/armv7/bootblock.inc

@@ -29,8 +29,6 @@
  * MA 02111-1307 USA
  */
 
-#include <system.h>
-
 .section ".bl1", "a", %progbits
 _bl1:
 	/* For now we have to live with a first stage boot loader

src/arch/armv7/include/system.h

@@ -1,26 +0,0 @@
-/* FIXME(dhendrix): This is split out from asm/system.h. */
-#ifndef SYSTEM_H_
-#define SYSTEM_H_
-
-/*
- * This is used to ensure the compiler did actually allocate the register we
- * asked it for some inline assembly sequences.  Apparently we can't trust
- * the compiler from one version to another so a bit of paranoia won't hurt.
- * This string is meant to be concatenated with the inline asm string and
- * will cause compilation to stop on mismatch.
- * (for details, see gcc PR 15089)
- */
-#define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
-
-#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
-
-#define arch_align_stack(x) (x)
-
-#ifndef __ASSEMBLER__
- /*
-  * FIXME: sdelay originally came from arch/arm/cpu/armv7/exynos5/setup.h in
-  * u-boot but does not seem specific to exynos5...
-  */
-void sdelay(unsigned long loops);
-#endif // __ASSEMBLY__
-#endif	/* SYSTEM_H_ */

src/arch/armv7/lib/Makefile.inc

@@ -5,7 +5,6 @@ bootblock-y += cache.c
 
 romstage-y += cache.c
 romstage-y += div0.c
-romstage-y += syslib.c
 romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c
 
 ramstage-y += div0.c

src/arch/armv7/lib/syslib.c

@@ -1,39 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- *
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <arch/io.h>
-#include <system.h>	/* FIXME: dumping ground for prototypes */
-
-/************************************************************
- * sdelay() - simple spin loop.  Will be constant time as
- *  its generally used in bypass conditions only.  This
- *  is necessary until timers are accessible.
- *
- *  not inline to increase chances its in cache when called
- *************************************************************/
-void sdelay(unsigned long loops)
-{
-	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
-			  "bne 1b":"=r" (loops):"0"(loops));
-}
-

src/cpu/armltd/cortex-a9/cache.c

@@ -12,7 +12,6 @@
  */
 
 #include <common.h>
-#include <system.h>
 #include <armv7.h>
 
 /*

src/cpu/samsung/exynos5250/clock_init.c

@@ -25,7 +25,6 @@
 #include <delay.h>
 #include <stdlib.h>
 #include <types.h>
-#include <system.h>
 
 #include <console/console.h>
 

src/cpu/samsung/exynos5250/dmc_common.c

@@ -24,12 +24,11 @@
 
 #include <arch/io.h>
 #include <assert.h>
-#include <common.h>
+#include <delay.h>
 #include <console/console.h>
 #include <cpu/samsung/exynos5250/setup.h>
 #include <cpu/samsung/exynos5250/dmc.h>
 #include <cpu/samsung/exynos5250/clock_init.h>
-#include <system.h>
 
 #include "clock_init.h"
 #include "setup.h"
@@ -75,7 +74,7 @@ int dmc_config_zq(struct mem_timings *mem,
 	 */
 	i = ZQ_INIT_TIMEOUT;
 	while ((readl(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
-		sdelay(100);
+		udelay(1);
 		i--;
 	}
 	if (!i)
@@ -84,7 +83,7 @@ int dmc_config_zq(struct mem_timings *mem,
 
 	i = ZQ_INIT_TIMEOUT;
 	while ((readl(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
-		sdelay(100);
+		udelay(1);
 		i--;
 	}
 	if (!i)
@@ -135,21 +134,27 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc)
 			 * delays? This one and the next were not there for
 			 * DDR3.
 			 */
-			sdelay(0x10000);
+			udelay(100);
 
 			/* Sending EMRS/MRS commands */
 			for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
 				writel(mem->direct_cmd_msr[i] | mask,
 				       &dmc->directcmd);
-				sdelay(0x10000);
+				udelay(100);
 			}
 
 			if (mem->send_zq_init) {
 				/* Sending ZQINIT command */
 				writel(DIRECT_CMD_ZQINIT | mask,
 				       &dmc->directcmd);
-
+				/*
-				sdelay(10000);
+				 * FIXME: This was originally sdelay(10000)
+				 * in the imported u-boot code. That may have
+				 * been meant to be sdelay(0x10000) since that
+				 * was used elsewhere in this function. Either
+				 * way seems to work, though.
+				 */
+				udelay(12);
 			}
 		}
 	}
@@ -168,7 +173,7 @@ void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc)
 
 			/* PALL (all banks precharge) CMD */
 			writel(DIRECT_CMD_PALL | mask, &dmc->directcmd);
-			sdelay(0x10000);
+			udelay(100);
 		}
 	}
 }

src/cpu/samsung/exynos5250/dmc_init_ddr3.c

@@ -23,12 +23,12 @@
  */
 
 #include <config.h>
+#include <delay.h>
 #include <arch/io.h>
 #include <console/console.h>
 //#include "clock.h"
 /* FIXME(dhendrix): untangle clock/clk ... */
 #include <cpu/samsung/exynos5-common/clock.h>
-#include <system.h>
 #include "clk.h"
 #include "cpu.h"
 #include "dmc.h"
@@ -44,6 +44,7 @@ static void reset_phy_ctrl(void)
 	writel(LPDDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl);
 	writel(LPDDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
 
+#if 0
 	/*
 	 * For proper memory initialization there should be a minimum delay of
 	 * 500us after the LPDDR3PHY_CTRL_PHY_RESET signal.
@@ -56,6 +57,8 @@ static void reset_phy_ctrl(void)
 	 * TODO(hatim.rv@samsung.com): Implement the delay using timer/counter
 	 */
 	sdelay(425000);
+#endif
+	udelay(500);
 }
 
 int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
@@ -236,7 +239,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
 			 * TODO(waihong): Comment on how long this take to
 			 * timeout
 			 */
-			sdelay(100);
+			udelay(1);
 			i--;
 		}
 		if (!i){