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soc/intel/baytrail/cpu.c: Align with Braswell 

This reduces the differences between Bay Trail and Braswell.

Tested with BUILD_TIMELESS=1, Google Ninja remains identical.

Change-Id: I9d9edd774143b0a98773b6d5de630d116cb6f0b1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43197
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-07-07 18:13:47 +02:00
parent 31929bf489
commit 1fb17d65cf
1 changed files with 3 additions and 4 deletions
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7
src/soc/intel/baytrail/cpu.c
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@ -13,14 +13,13 @@
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <reg_script.h> #include <reg_script.h>
#include <soc/iosf.h> #include <soc/iosf.h>
#include <soc/msr.h> #include <soc/msr.h>
#include <soc/pattrs.h> #include <soc/pattrs.h>
#include <soc/ramstage.h> #include <soc/ramstage.h>
/* Core level MSRs */ /* Core level MSRs */
const struct reg_script core_msr_script[] = { static const struct reg_script core_msr_script[] = {
/* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */
REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008),
REG_MSR_RMW(MSR_POWER_MISC, ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0), REG_MSR_RMW(MSR_POWER_MISC, ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0),
@ -31,7 +30,7 @@ const struct reg_script core_msr_script[] = {
REG_SCRIPT_END REG_SCRIPT_END
}; };
static void baytrail_core_init(struct device *cpu) static void soc_core_init(struct device *cpu)
{ {
printk(BIOS_DEBUG, "Init BayTrail core.\n"); printk(BIOS_DEBUG, "Init BayTrail core.\n");
@ -54,7 +53,7 @@ static void baytrail_core_init(struct device *cpu)
} }
static struct device_operations cpu_dev_ops = { static struct device_operations cpu_dev_ops = {
.init = baytrail_core_init, .init = soc_core_init,
}; };
static const struct cpu_device_id cpu_table[] = { static const struct cpu_device_id cpu_table[] = {