C32 legacy code: change CONFIG_CPU_AMD_SOCKET_C32 to CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA
Currently the C32 has some legacy boards which use the old C32 code. We need to seperate them. CONFIG_CPU_AMD_SOCKET_C32 was used in legacy code before. But it is not a good idea, so we change the code as follows: So we use CONFIG_CPU_AMD_SOCKET_C32 to identify mainboard which uses agesa code, and use CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA to identify mainboard which uses legacy code. Change-Id: If6114bf8912e78b7732f25a1adfb2e4d8eb10ee4 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1497 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
parent
fec5b647fc
commit
1fb49dfa5e
|
@ -7,7 +7,7 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2) += socket_AM2
|
||||||
subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2R2) += socket_AM2r2
|
subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2R2) += socket_AM2r2
|
||||||
subdirs-$(CONFIG_CPU_AMD_SOCKET_AM3) += socket_AM3
|
subdirs-$(CONFIG_CPU_AMD_SOCKET_AM3) += socket_AM3
|
||||||
subdirs-$(CONFIG_CPU_AMD_SOCKET_ASB2) += socket_ASB2
|
subdirs-$(CONFIG_CPU_AMD_SOCKET_ASB2) += socket_ASB2
|
||||||
subdirs-$(CONFIG_CPU_AMD_SOCKET_C32) += socket_C32
|
subdirs-$(CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA) += socket_C32
|
||||||
subdirs-$(CONFIG_CPU_AMD_GEODE_GX1) += geode_gx1
|
subdirs-$(CONFIG_CPU_AMD_GEODE_GX1) += geode_gx1
|
||||||
subdirs-$(CONFIG_CPU_AMD_GEODE_GX2) += geode_gx2
|
subdirs-$(CONFIG_CPU_AMD_GEODE_GX2) += geode_gx2
|
||||||
subdirs-$(CONFIG_CPU_AMD_GEODE_LX) += geode_lx
|
subdirs-$(CONFIG_CPU_AMD_GEODE_LX) += geode_lx
|
||||||
|
|
|
@ -1,4 +1,4 @@
|
||||||
config CPU_AMD_SOCKET_C32
|
config CPU_AMD_SOCKET_C32_NON_AGESA
|
||||||
bool
|
bool
|
||||||
select CPU_AMD_MODEL_10XXX
|
select CPU_AMD_MODEL_10XXX
|
||||||
select HT3_SUPPORT
|
select HT3_SUPPORT
|
||||||
|
@ -8,30 +8,30 @@ config CPU_AMD_SOCKET_C32
|
||||||
config CPU_SOCKET_TYPE
|
config CPU_SOCKET_TYPE
|
||||||
hex
|
hex
|
||||||
default 0x14
|
default 0x14
|
||||||
depends on CPU_AMD_SOCKET_C32
|
depends on CPU_AMD_SOCKET_C32_NON_AGESA
|
||||||
|
|
||||||
config EXT_RT_TBL_SUPPORT
|
config EXT_RT_TBL_SUPPORT
|
||||||
bool
|
bool
|
||||||
default n
|
default n
|
||||||
depends on CPU_AMD_SOCKET_C32
|
depends on CPU_AMD_SOCKET_C32_NON_AGESA
|
||||||
|
|
||||||
config EXT_CONF_SUPPORT
|
config EXT_CONF_SUPPORT
|
||||||
bool
|
bool
|
||||||
default n
|
default n
|
||||||
depends on CPU_AMD_SOCKET_C32
|
depends on CPU_AMD_SOCKET_C32_NON_AGESA
|
||||||
|
|
||||||
config CBB
|
config CBB
|
||||||
hex
|
hex
|
||||||
default 0x0
|
default 0x0
|
||||||
depends on CPU_AMD_SOCKET_C32
|
depends on CPU_AMD_SOCKET_C32_NON_AGESA
|
||||||
|
|
||||||
config CDB
|
config CDB
|
||||||
hex
|
hex
|
||||||
default 0x18
|
default 0x18
|
||||||
depends on CPU_AMD_SOCKET_C32
|
depends on CPU_AMD_SOCKET_C32_NON_AGESA
|
||||||
|
|
||||||
config XIP_ROM_SIZE
|
config XIP_ROM_SIZE
|
||||||
hex
|
hex
|
||||||
default 0x80000
|
default 0x80000
|
||||||
depends on CPU_AMD_SOCKET_C32
|
depends on CPU_AMD_SOCKET_C32_NON_AGESA
|
||||||
|
|
||||||
|
|
|
@ -3,7 +3,7 @@ if BOARD_SUPERMICRO_H8SCM_FAM10
|
||||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||||
def_bool y
|
def_bool y
|
||||||
select ARCH_X86
|
select ARCH_X86
|
||||||
select CPU_AMD_SOCKET_C32
|
select CPU_AMD_SOCKET_C32_NON_AGESA
|
||||||
select DIMM_DDR3
|
select DIMM_DDR3
|
||||||
select DIMM_REGISTERED
|
select DIMM_REGISTERED
|
||||||
select NORTHBRIDGE_AMD_AMDFAM10
|
select NORTHBRIDGE_AMD_AMDFAM10
|
||||||
|
|
Loading…
Reference in New Issue