diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig
index eaae86ce8c..f723a6c10d 100644
--- a/src/mainboard/google/rush/Kconfig
+++ b/src/mainboard/google/rush/Kconfig
@@ -95,4 +95,12 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
 	hex
 	default 1
 
+config DRAM_DMA_START
+       hex
+       default 0xc0000000
+
+config DRAM_DMA_SIZE
+       hex
+       default 0x00200000
+
 endif # BOARD_GOOGLE_RUSH
diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c
index c4b0b441c4..35417f07ce 100644
--- a/src/mainboard/google/rush/mainboard.c
+++ b/src/mainboard/google/rush/mainboard.c
@@ -17,9 +17,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
+#include <arch/mmu.h>
 #include <device/device.h>
 #include <boot/coreboot_tables.h>
 
+#include <memrange.h>
 #include <soc/clock.h>
 #include <soc/nvidia/tegra132/clk_rst.h>
 #include <soc/nvidia/tegra132/spi.h>
@@ -86,3 +88,22 @@ struct chip_operations mainboard_ops = {
         .name   = "rush",
         .enable_dev = mainboard_enable,
 };
+
+
+void mainboard_add_memory_ranges(struct memranges *map)
+{
+	/* Create non-cacheable region for DMA operations. */
+	memranges_insert(map, CONFIG_DRAM_DMA_START, CONFIG_DRAM_DMA_SIZE,
+			 MA_MEM  | MA_MEM_NC | MA_NS | MA_RW);
+}
+
+void lb_board(struct lb_header *header)
+{
+	struct lb_range *dma;
+
+	dma = (struct lb_range *)lb_new_record(header);
+	dma->tag = LB_TAB_DMA;
+	dma->size = sizeof(*dma);
+	dma->range_start = CONFIG_DRAM_DMA_START;
+	dma->range_size = CONFIG_DRAM_DMA_SIZE;
+}