google/lars: SPD change for Proto board

Update Memory ID for Proto board
Update detection of single/dual channel memory to use SPD Index (Memory ID)
Remove boardid.h as it is no longer needed

BUG=None
BRANCH=None
TEST=Build and Boot Lars (Proto)

Change-Id: I100b0fec4bf555c261e30140109cb0f36576130c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 24a4fddf4f1a4441fca8783cfa451e220ff986d8
Original-Change-Id: I636e881cb3fb9a0056edea2bc34a861a59b91c8f
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313903
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12593
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
david 2015-11-23 20:24:54 +08:00 committed by Patrick Georgi
parent a009158bf9
commit 1fc5d1f01a
4 changed files with 12 additions and 49 deletions

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@ -1,27 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*/
#ifndef _BOARDID_H_
#define _BOARDID_H_
#define SCRD_SKU1 0x3
#define SCRD_SKU2 0x4
#define SCRD_SKU3 0x1
#define SCRD_SKU4 0x2
#define SCRD_SKU5 0x5
#define SCRD_SKU6 0x6
#endif

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@ -18,10 +18,10 @@ romstage-y += spd.c
SPD_BIN = $(obj)/spd.bin
SPD_SOURCES = hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866 # 0b0000
SPD_SOURCES += hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866 # 0b0001
SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF-1G-1866 # 0b0010
SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF-2G-1866 # 0b0011
SPD_SOURCES = hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866 # 0b0000 Single Channel 2GB
SPD_SOURCES += hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866 # 0b0001 Dual Channel 8GB
SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF-1G-1866 # 0b0010 Dual Channel 4GB
SPD_SOURCES += empty # 0b0011
SPD_SOURCES += empty # 0b0100
SPD_SOURCES += empty # 0b0101
SPD_SOURCES += empty # 0b0110

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@ -15,14 +15,12 @@
*/
#include <arch/byteorder.h>
#include <boardid.h>
#include <cbfs.h>
#include <console/console.h>
#include <soc/pei_data.h>
#include <soc/romstage.h>
#include <string.h>
#include "../boardid.h"
#include "spd.h"
static void mainboard_print_spd_info(uint8_t spd[])
@ -81,17 +79,11 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
{
char *spd_file;
size_t spd_file_len;
int spd_index, sku_id;
int spd_index, spd_span;
spd_index = pei_data->mem_cfg_id;
/*
* XXX: This is incorrect usage.The Board ID should be the revision ID
* and not SKU ID but on SCRD it indicates SKU.
*/
sku_id = board_id();
printk(BIOS_INFO, "SPD index %d\n", spd_index);
printk(BIOS_INFO, "Board ID %d\n", sku_id);
/* Load SPD data from CBFS */
spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
@ -110,16 +102,13 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
}
/* Assume same memory in both channels */
spd_index *= SPD_LEN;
memcpy(pei_data->spd_data[0][0], spd_file + spd_index, SPD_LEN);
/*
* XXX: This is incorrect usage. mem_cfg should be used here instead of
* SKU ID. The current implementation of mem_config does not
* support channel population.
*/
spd_span = spd_index * SPD_LEN;
memcpy(pei_data->spd_data[0][0], spd_file + spd_span, SPD_LEN);
if (sku_id != SCRD_SKU1)
memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN);
if (spd_index != HYNIX_SINGLE_CHAN) {
memcpy(pei_data->spd_data[1][0], spd_file + spd_span, SPD_LEN);
printk(BIOS_INFO, "Dual channel SPD detected writing second channel\n");
}
/* Make sure a valid SPD was found */
if (pei_data->spd_data[0][0][0] == 0)

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@ -30,4 +30,5 @@
#define SPD_PART_LEN 18
#define SPD_MANU_OFF 148
#define HYNIX_SINGLE_CHAN 0x0
#endif