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soc/intel/jasperlake: Make use of is_devfn_enabled() function 

1. Replace all pcidev_path_on_root() and is_dev_enabled() functions
combination with is_devfn_enabled().
2. Remove unused local variable of device structure type (struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled()
call.

TEST=Able to build and boot without any regression seen on dedede

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I4919a1ec02df50bc41fd66d5f3a352108a7aa04c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Subrata Banik 2021-06-09 03:57:41 +05:30
parent 6f910e24b6
commit 1fcfe3d96a
3 changed files with 11 additions and 24 deletions
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6
src/soc/intel/jasperlake/acpi.c
View File

@ -172,11 +172,10 @@ uint32_t soc_read_sci_irq_select(void)
static unsigned long soc_fill_dmar(unsigned long current)
{
const struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
if (is_dev_enabled(igfx_dev) && gfxvtbar && gfxvten) {
if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) {
unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
@ -185,11 +184,10 @@ static unsigned long soc_fill_dmar(unsigned long current)
acpi_dmar_drhd_fixup(tmp, current);
}
const struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU);
uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK;
bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED;
if (is_dev_enabled(ipu_dev) && ipuvtbar && ipuvten) {
if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) {
unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar);

16
src/soc/intel/jasperlake/fsp_params.c
View File

@ -78,8 +78,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->GraphicsConfigPtr = (uintptr_t)vbt_get();
/* Check if IGD is present and fill Graphics init param accordingly */
dev = pcidev_path_on_root(SA_DEVFN_IGD);
params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev);
params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
params->PavpEnable = CONFIG(PAVP);
@ -147,8 +146,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
}
/* SATA */
dev = pcidev_path_on_root(PCH_DEVFN_SATA);
params->SataEnable = is_dev_enabled(dev);
params->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA);
if (params->SataEnable) {
params->SataMode = config->SataMode;
params->SataSalpSupport = config->SataSalpSupport;
@ -169,21 +167,18 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->ImonOffset[0] = config->ImonOffset;
/* SDCard related configuration */
dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);
params->ScsSdCardEnabled = is_dev_enabled(dev);
params->ScsSdCardEnabled = is_devfn_enabled(PCH_DEVFN_SDCARD);
if (params->ScsSdCardEnabled)
params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh;
/* Enable Processor Thermal Control */
dev = pcidev_path_on_root(SA_DEVFN_DPTF);
params->Device4Enable = is_dev_enabled(dev);
params->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF);
/* Set TccActivationOffset */
params->TccActivationOffset = config->tcc_offset;
/* eMMC configuration */
dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
params->ScsEmmcEnabled = is_dev_enabled(dev);
params->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC);
if (params->ScsEmmcEnabled)
params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
@ -192,7 +187,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
if (dev) {
if (!xdci_can_enable())
dev->enabled = 0;
params->XdciEnable = dev->enabled;
} else {
params->XdciEnable = 0;

13
src/soc/intel/jasperlake/romstage/fsp_params.c
View File

@ -14,15 +14,13 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
const struct soc_intel_jasperlake_config *config)
{
unsigned int i;
const struct device *dev;
uint32_t mask = 0;
/*
* If IGD is enabled, set IGD stolen size to 60MB.
* Otherwise, skip IGD init in FSP.
*/
dev = pcidev_path_on_root(SA_DEVFN_IGD);
m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_dev_enabled(dev);
m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0;
m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
@ -60,16 +58,14 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO;
/* TraceHub configuration */
dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB);
if (is_dev_enabled(dev) && config->TraceHubMode) {
if (is_devfn_enabled(PCH_DEVFN_TRACEHUB) && config->TraceHubMode) {
m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB;
m_cfg->PchTraceHubMode = config->TraceHubMode;
m_cfg->CpuTraceHubMode = config->TraceHubMode;
}
/* IPU configuration */
dev = pcidev_path_on_root(SA_DEVFN_IPU);
m_cfg->SaIpuEnable = is_dev_enabled(dev);
m_cfg->SaIpuEnable = is_devfn_enabled(SA_DEVFN_IPU);
/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
@ -106,8 +102,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->DdiPortCDdc = config->DdiPortCDdc;
/* Audio */
dev = pcidev_path_on_root(PCH_DEVFN_HDA);
m_cfg->PchHdaEnable = is_dev_enabled(dev);
m_cfg->PchHdaEnable = is_devfn_enabled(PCH_DEVFN_HDA);
m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;
m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable;