diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig
index 9ddd9fde5f..c95da355c6 100644
--- a/src/mainboard/google/rex/Kconfig
+++ b/src/mainboard/google/rex/Kconfig
@@ -25,6 +25,7 @@ config BOARD_GOOGLE_REX_COMMON
 	select MAINBOARD_DISABLE_STAGE_CACHE
 	select MAINBOARD_HAS_TPM2
 	select PMC_IPC_ACPI_INTERFACE
+	select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT
 	select SOC_INTEL_CSE_LITE_SKU
 	select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2
 	select SOC_INTEL_CSE_SEND_EOP_ASYNC
diff --git a/src/mainboard/google/rex/mainboard.c b/src/mainboard/google/rex/mainboard.c
index a0dba44e4c..d59d3d49e3 100644
--- a/src/mainboard/google/rex/mainboard.c
+++ b/src/mainboard/google/rex/mainboard.c
@@ -41,6 +41,12 @@ static void mainboard_init(void *chip_info)
 	fw_config_gpio_padbased_override(padbased_table);
 	gpio_configure_pads_with_padbased(padbased_table);
 	free(padbased_table);
+	variant_devtree_update();
+}
+
+void __weak variant_devtree_update(void)
+{
+	/* Override dev tree settings per board */
 }
 
 void __weak variant_generate_s0ix_hook(enum s0ix_entry entry)
diff --git a/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h
index 6bb52e28a9..afed754438 100644
--- a/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h
@@ -31,4 +31,7 @@ enum s0ix_entry {
 
 void variant_generate_s0ix_hook(enum s0ix_entry entry);
 
+/* Modify devictree settings during ramstage */
+void variant_devtree_update(void);
+
 #endif /*__BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc b/src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc
index fd45b948ff..bb3620adae 100644
--- a/src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc
+++ b/src/mainboard/google/rex/variants/baseboard/rex/Makefile.inc
@@ -1 +1,3 @@
 romstage-y += memory.c
+
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c
new file mode 100644
index 0000000000..aee3d888a1
--- /dev/null
+++ b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <device/pci_ids.h>
+#include <intelblocks/power_limit.h>
+
+/*
+ * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts),
+ * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
+ * Following values are for performance config as per document #640982
+ */
+const struct cpu_tdp_power_limits limits[] = {
+	{
+		.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
+		.cpu_tdp = 15,
+		.pl1_min_power = 10000,
+		.pl1_max_power = 15000,
+		.pl2_min_power = 57000,
+		.pl2_max_power = 57000,
+		.pl4_power = 114000
+	},
+};
+
+void variant_devtree_update(void)
+{
+	size_t total_entries = ARRAY_SIZE(limits);
+	variant_update_cpu_power_limits(limits, total_entries);
+}