From 1ffec679fe16af01340f193df45a64d538ba63a8 Mon Sep 17 00:00:00 2001
From: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Date: Mon, 9 May 2022 16:15:43 +0800
Subject: [PATCH] mb/google/brya/var/agah: Enable PCIe RP 3 for LAN

Using CLKREQ 4 and CLKSRC 4

BUG=b:210970640
BRANCH=NONE
TEST=emerge-draco coreboot chromeos-bootimage

Change-Id: Ie0e362013551036a03ef69a98c6f1793e0e75c41
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
---
 src/mainboard/google/brya/variants/agah/overridetree.cb | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb
index 70bc09289d..01f0252258 100644
--- a/src/mainboard/google/brya/variants/agah/overridetree.cb
+++ b/src/mainboard/google/brya/variants/agah/overridetree.cb
@@ -157,6 +157,12 @@ chip soc/intel/alderlake
 			end
 		end
 		device ref pcie_rp3 on
+			# Enable PCIE 3 using clk 4
+			register "pch_pcie_rp[PCH_RP(3)]" = "{
+				.clk_src = 4,
+				.clk_req = 4,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
 			chip drivers/net
 				register "customized_leds" = "0x05af"
 				register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D2)"