Whitespace and other code cleanup in peperation for AMD Barcelona support.
Signed-off-by: Marc Jones <marc.jones@amd.com> Reviewed-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Myles Watson <myles@pel.cs.byu.edu> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marc Jones
parent
244dd82fd6
commit
2006b38fed
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@ -1,8 +1,25 @@
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/* by yhlu 6.2005 */
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/* yhlu 2005.12 make it support HDT Memory Debuggers with Disassmbly, please select the PCI Bus mem for Phys Type*/
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/* yhlu 2006.3 copy data from cache to ram and reserve 0x1000 for global variables */
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/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2005-2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define CacheSize DCACHE_RAM_SIZE
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#define CacheBase (0xd0000 - CacheSize)
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/* leave some space for global variable to pass to RAM stage */
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#define GlobalVarSize DCACHE_RAM_GLOBAL_VAR_SIZE
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@ -12,30 +29,31 @@
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/* Save the BIST result */
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movl %eax, %ebp
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/*for normal part %ebx already contain cpu_init_detected from fallback call */
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/* for normal part %ebx already contain cpu_init_detected from fallback call */
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cache_as_ram_setup:
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/* hope we can skip the double set for normal part */
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#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE==1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE==1))
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#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))
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/* check if cpu_init_detected */
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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andl $0x00000800, %eax
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andl $(1 << 11), %eax
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movl %eax, %ebx /* We store the status */
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/* Set MtrrFixDramModEn for clear fixed mtrr */
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enable_fixed_mtrr_dram_modify:
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movl $SYSCFG_MSR, %ecx
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rdmsr
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andl $(~(SYSCFG_MSR_MtrrFixDramEn|SYSCFG_MSR_MtrrVarDramEn)), %eax
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andl $(~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn)), %eax
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orl $SYSCFG_MSR_MtrrFixDramModEn, %eax
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wrmsr
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/*Clear all MTRRs */
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/* Clear all MTRRs */
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xorl %edx, %edx
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movl $fixed_mtrr_msr, %esi
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clear_fixed_var_mtrr:
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lodsl (%esi), %eax
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testl %eax, %eax
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@ -50,7 +68,7 @@ clear_fixed_var_mtrr_out:
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#if CacheSize == 0x10000
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/* enable caching for 64K using fixed mtrr */
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movl $0x268, %ecx /* fix4k_c0000*/
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movl $0x268, %ecx /* fix4k_c0000 */
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movl $0x06060606, %eax /* WB IO type */
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movl %eax, %edx
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wrmsr
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@ -60,22 +78,21 @@ clear_fixed_var_mtrr_out:
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#if CacheSize == 0xc000
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/* enable caching for 16K using fixed mtrr */
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movl $0x268, %ecx /* fix4k_c4000*/
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movl $0x268, %ecx /* fix4k_c4000 */
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movl $0x06060606, %edx /* WB IO type */
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xorl %eax, %eax
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wrmsr
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/* enable caching for 32K using fixed mtrr */
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movl $0x269, %ecx /* fix4k_c8000*/
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movl $0x269, %ecx /* fix4k_c8000 */
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movl $0x06060606, %eax /* WB IO type */
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movl %eax, %edx
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wrmsr
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#endif
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#if CacheSize == 0x8000
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/* enable caching for 32K using fixed mtrr */
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movl $0x269, %ecx /* fix4k_c8000*/
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movl $0x269, %ecx /* fix4k_c8000 */
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movl $0x06060606, %eax /* WB IO type */
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movl %eax, %edx
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wrmsr
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@ -84,15 +101,15 @@ clear_fixed_var_mtrr_out:
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#if CacheSize < 0x8000
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/* enable caching for 16K/8K/4K using fixed mtrr */
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movl $0x269, %ecx /* fix4k_cc000*/
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#if CacheSize == 0x4000
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#if CacheSize == 0x4000
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movl $0x06060606, %edx /* WB IO type */
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#endif
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#if CacheSize == 0x2000
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#endif
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#if CacheSize == 0x2000
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movl $0x06060000, %edx /* WB IO type */
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#endif
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#if CacheSize == 0x1000
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#endif
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#if CacheSize == 0x1000
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movl $0x06000000, %edx /* WB IO type */
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#endif
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#endif
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xorl %eax, %eax
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wrmsr
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#endif
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@ -105,10 +122,10 @@ clear_fixed_var_mtrr_out:
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#endif /* USE_FAILOVER_IMAGE == 1*/
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#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 0)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE==0))
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#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 0)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 0))
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/* disable cache */
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movl %cr0, %eax
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orl $(0x1<<30),%eax
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orl $(1 << 30),%eax
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movl %eax, %cr0
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#endif
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@ -123,12 +140,12 @@ clear_fixed_var_mtrr_out:
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wrmsr
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movl $0x203, %ecx
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movl $((1<<(CPU_ADDR_BITS-32))-1), %edx /* AMD 40 bit */
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movl $((1 << (CPU_ADDR_BITS - 32)) - 1), %edx /* AMD 40 bit for K8, 48 bit for GH */
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movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
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wrmsr
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#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
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#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE==1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE==1))
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#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))
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/* Set the default memory type and enable fixed and variable MTRRs */
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movl $MTRRdefType_MSR, %ecx
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xorl %edx, %edx
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@ -145,32 +162,31 @@ clear_fixed_var_mtrr_out:
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/* enable cache */
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movl %cr0, %eax
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andl $0x9fffffff,%eax
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andl $0x9fffffff, %eax
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movl %eax, %cr0
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#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE==1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE==1))
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#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))
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/* Read the range with lodsl*/
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cld
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movl $CacheBase, %esi
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movl $(CacheSize>>2), %ecx
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rep
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lodsl
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movl $(CacheSize >> 2), %ecx
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rep lodsl
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/* Clear the range */
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movl $CacheBase, %edi
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movl $(CacheSize>>2), %ecx
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movl $(CacheSize >> 2), %ecx
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xorl %eax, %eax
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rep
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stosl
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rep stosl
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#endif /*USE_FAILOVER_IMAGE == 1*/
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/* set up the stack pointer */
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movl $(CacheBase+CacheSize - GlobalVarSize), %eax
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movl $(CacheBase + CacheSize - GlobalVarSize), %eax
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movl %eax, %esp
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/* Restore the BIST result */
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movl %ebp, %eax
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/* We need to set ebp ? No need */
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movl %esp, %ebp
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pushl %ebx /* init detected */
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@ -193,4 +209,5 @@ var_iorr_msr:
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mem_top:
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.long 0xC001001A, 0xC001001D
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.long 0x000 /* NULL, end of table */
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cache_as_ram_setup_out:
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@ -1,43 +1,22 @@
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/*============================================================================
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Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
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This software and any related documentation (the "Materials") are the
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confidential proprietary information of AMD. Unless otherwise provided in a
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software agreement specifically licensing the Materials, the Materials are
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provided in confidence and may not be distributed, modified, or reproduced in
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whole or in part by any means.
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LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY
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EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
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WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY
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PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR
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USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY
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DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
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BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR
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INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION
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OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
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LIMITATION MAY NOT APPLY TO YOU.
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AMD does not assume any responsibility for any errors which may appear in the
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Materials nor any responsibility to support or update the Materials. AMD
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retains the right to modify the Materials at any time, without notice, and is
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not obligated to provide such modified Materials to you.
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NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
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further information, software, technical information, know-how, or show-how
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available to you.
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U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED
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RIGHTS." Use, duplication, or disclosure by the Government is subject to the
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restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or
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its successor. Use of the Materials by the Government constitutes
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acknowledgement of AMD's proprietary rights in them.
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============================================================================*/
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//@DOC
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// microcode.c
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/*
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$1.0$
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*/
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// Description: microcode patch support for k8
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// by yhlu
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//
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//============================================================================
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdint.h>
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#include <console/console.h>
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#include <cpu/cpu.h>
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@ -46,35 +25,35 @@ $1.0$
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#include <cpu/x86/cache.h>
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struct microcode {
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uint32_t date_code;
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uint32_t patch_id;
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u32 date_code;
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u32 patch_id;
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uint16_t m_patch_data_id;
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uint8_t m_patch_data_len;
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uint8_t init_flag;
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u16 m_patch_data_id;
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u8 m_patch_data_len;
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u8 init_flag;
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uint32_t m_patch_data_cksum;
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u32 m_patch_data_cksum;
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uint32_t nb_dev_id;
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uint32_t ht_io_hub_dev_id;
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u32 nb_dev_id;
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u32 ht_io_hub_dev_id;
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uint16_t processor_rev_id;
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uint8_t ht_io_hub_rev_id;
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uint8_t nb_rev_id;
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u16 processor_rev_id;
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u8 ht_io_hub_rev_id;
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u8 nb_rev_id;
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uint8_t bios_api_rev;
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uint8_t resv1[3];
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u8 bios_api_rev;
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u8 resv1[3];
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uint32_t match_reg[8];
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u32 match_reg[8];
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uint8_t m_patch_data[896];
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uint8_t resv2[896];
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u8 m_patch_data[896];
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u8 resv2[896];
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uint8_t x86_code_present;
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uint8_t x86_code_entry[191];
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u8 x86_code_present;
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u8 x86_code_entry[191];
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};
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static int need_apply_patch(struct microcode *m, unsigned equivalent_processor_rev_id)
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static int need_apply_patch(struct microcode *m, u32 equivalent_processor_rev_id)
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{
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if (m->processor_rev_id != equivalent_processor_rev_id) return 0;
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@ -97,9 +76,9 @@ static int need_apply_patch(struct microcode *m, unsigned equivalent_processor_r
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}
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void amd_update_microcode(void *microcode_updates, unsigned equivalent_processor_rev_id)
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void amd_update_microcode(void *microcode_updates, u32 equivalent_processor_rev_id)
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{
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unsigned int patch_id, new_patch_id;
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u32 patch_id, new_patch_id;
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struct microcode *m;
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char *c;
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msr_t msr;
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@ -117,7 +96,7 @@ void amd_update_microcode(void *microcode_updates, unsigned equivalent_processor
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//apply patch
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msr.hi = 0;
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msr.lo = (uint32_t)m;
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msr.lo = (u32)m;
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wrmsr(0xc0010020, msr);
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