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amdblocks/pci: add common implementation of MMCONF enabling 

Add common function to enable PCI MMCONF base address. Use the common
function in stoneyridge bootblock.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I1bb8b22b282584c421a9fffa3322b2a8e406d037
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Michał Żygowski 2019-12-06 12:07:52 +01:00 committed by Patrick Georgi
parent a244d5edd4
commit 200d213d1b
4 changed files with 50 additions and 9 deletions
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19
src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h Normal file
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@ -0,0 +1,19 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __AMDBLOCKS_PCI_MMCONF_H__
#define __AMDBLOCKS_PCI_MMCONF_H__
void enable_pci_mmconf(void);
#endif

5
src/soc/amd/common/block/pci/Makefile.inc
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@ -1,5 +1,4 @@
ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI),y)
ramstage-y += amd_pci_util.c
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI) += amd_pci_util.c
endif
all-y += amd_pci_mmconf.c

27
src/soc/amd/common/block/pci/amd_pci_mmconf.c Normal file
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@ -0,0 +1,27 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <amdblocks/amd_pci_mmconf.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
void enable_pci_mmconf(void)
{
msr_t mmconf;
mmconf.hi = 0;
mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN
| fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT;
wrmsr(MMIO_CONF_BASE, mmconf);
}

8
src/soc/amd/stoneyridge/bootblock/bootblock.c
View File

@ -24,6 +24,7 @@
#include <bootblock_common.h>
#include <amdblocks/agesawrapper.h>
#include <amdblocks/agesawrapper_call.h>
#include <amdblocks/amd_pci_mmconf.h>
#include <amdblocks/biosram.h>
#include <soc/pci_devs.h>
#include <soc/cpu.h>
@ -42,15 +43,9 @@
/* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */
static void amd_initmmio(void)
{
msr_t mmconf;
msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
int mtrr;
mmconf.hi = 0;
mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN
| fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT;
wrmsr(MMIO_CONF_BASE, mmconf);
/*
* todo: AGESA currently writes variable MTRRs. Once that is
* corrected, un-hardcode this MTRR.
@ -75,6 +70,7 @@ static void amd_initmmio(void)
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
enable_pci_mmconf();
amd_initmmio();
/*
* Call lib/bootblock.c main with BSP, shortcut for APs