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This board (http://www.ieiworld.com/en/product_IPC.asp?model=PCISA-LX) 

is based on amd-lx800/cs5536.

Tutorial: http://www.coreboot.org/IEI_LX_800_Build_Tutorial

Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3261 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Nikolay Petukhov 2008-04-24 13:37:01 +00:00 committed by Uwe Hermann
parent 20ba8eb7ab
commit 202625e61f
7 changed files with 783 additions and 0 deletions
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148
src/mainboard/iei/pcisa-lx-800-r10/Config.lb Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
else
default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
default ROM_SECTION_OFFSET = 0
end
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
default XIP_ROM_SIZE = 64 * 1024
default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
arch i386 end
driver mainboard.o
if HAVE_PIRQ_TABLE
object irq_tables.o
end
if USE_DCACHE_RAM
# Compile cache_as_ram.c to auto.inc.
makerule ./cache_as_ram_auto.inc
# depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
depends "$(MAINBOARD)/cache_as_ram_auto.c"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
end
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
if USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
# mainboardinit ./failover.inc
end
mainboardinit cpu/x86/fpu/enable_fpu.inc
if USE_DCACHE_RAM
mainboardinit cpu/amd/model_lx/cache_as_ram.inc
mainboardinit ./cache_as_ram_auto.inc
end
dir /pc80
config chip.h
chip northbridge/amd/lx
device pci_domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Graphics
chip southbridge/amd/cs5536
# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
# SIRQ Mode = Active(Quiet) mode. Save power....
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
register "lpc_serirq_enable" = "0x000010da"
register "lpc_serirq_polarity" = "0x0000EF25"
register "lpc_serirq_mode" = "1"
register "enable_gpio_int_route" = "0x0D0C0700"
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
register "enable_USBP4_device" = "1" # 0: host, 1:device
register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
register "com1_enable" = "0"
register "com1_address" = "0x3F8"
register "com1_irq" = "4"
register "com2_enable" = "0"
register "com2_address" = "0x2F8"
register "com2_irq" = "3"
register "unwanted_vpci[0]" = "0" # End of list has a zero
device pci 9.0 on end # Slot1
device pci a.0 on end # Slot2
device pci b.0 on end # Slot3
device pci c.0 on end # Slot4
device pci e.0 on end # Ethernet 0
device pci 10.0 on end # Ethernet 1
device pci 11.0 on end # SATA
device pci f.0 on # ISA Bridge
chip superio/winbond/w83627hf
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 on # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b off end # HW Monitor
end
end
device pci f.2 on end # IDE Controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
end
end
# APIC cluster is late CPU init.
device apic_cluster 0 on
chip cpu/amd/model_lx
device apic 0 on end
end
end
end

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src/mainboard/iei/pcisa-lx-800-r10/Options.lb Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses CONFIG_ROM_PAYLOAD
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESS
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses PAYLOAD_SIZE
uses _ROMBASE
uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_UDELAY_IO
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses CONFIG_VIDEO_MB
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses PIRQ_ROUTE
default ROM_SIZE = 256 * 1024
default CONFIG_CONSOLE_VGA = 0
default CONFIG_VIDEO_MB = 8
default CONFIG_PCI_ROM_RUN = 0
default HAVE_FALLBACK_BOOT = 1
default HAVE_MP_TABLE = 0
default HAVE_HARD_RESET = 0
default CONFIG_UDELAY_IO = 1
default HAVE_PIRQ_TABLE = 1
default IRQ_SLOT_COUNT = 9
default PIRQ_ROUTE = 1
default HAVE_OPTION_TABLE = 0
default ROM_IMAGE_SIZE = 64 * 1024
default FALLBACK_SIZE = 128 * 1024
default USE_DCACHE_RAM = 1
default DCACHE_RAM_BASE = 0xc8000
default DCACHE_RAM_SIZE = 32 * 1024
default STACK_SIZE = 8 * 1024
default HEAP_SIZE = 16 * 1024
# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
default _RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
default CROSS_COMPILE = ""
default CC = "$(CROSS_COMPILE)gcc -m32"
default HOSTCC = "gcc"
default CONFIG_CONSOLE_SERIAL8250 = 1
default TTYS0_BAUD = 115200
default TTYS0_BASE = 0x3f8
default TTYS0_LCS = 0x3
default DEFAULT_CONSOLE_LOGLEVEL=8
default MAXIMUM_CONSOLE_LOGLEVEL=8
end

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src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#define POST_CODE(x) outb(x, 0x80)
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
static inline int spd_read_byte(unsigned int device, unsigned int address)
{
return smbus_read_byte(device, address);
}
#define ManualConf 1 /* Do automatic strapped PLL config */
//#define PLLMSRhi 0x0000059C /* CPU and GLIU mult/div 500/400*/
//#define PLLMSRhi 0x0000049C /* CPU and GLIU mult/div 500/333*/
#define PLLMSRhi 0x0000039C /* CPU and GLIU mult/div 500/266*/
//0x0000059C 0000 0000 0000 0000 0000 |0101 1|0|01 110|0
/* Hold Count - how long we will sit in reset */
#define PLLMSRlo 0x00DE6000
#define DIMM0 0xA0
#define DIMM1 0xA2
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
#include "sdram/generic_sdram.c"
#include "cpu/amd/model_lx/cpureginit.c"
#include "cpu/amd/model_lx/syspreinit.c"
static void msr_init(void)
{
msr_t msr;
/* Setup access to the cache for under 1MB. */
msr.hi = 0x24fffc02;
msr.lo = 0x1000A000; /* 0-A0000 write back */
wrmsr(CPU_RCONF_DEFAULT, msr);
msr.hi = 0x0; /* Write back */
msr.lo = 0x0;
wrmsr(CPU_RCONF_A0_BF, msr);
wrmsr(CPU_RCONF_C0_DF, msr);
wrmsr(CPU_RCONF_E0_FF, msr);
/* Setup access to the cache for under 640K. Note MC not setup yet. */
msr.hi = 0x20000000;
msr.lo = 0xfff80;
wrmsr(MSR_GLIU0 + 0x20, msr);
msr.hi = 0x20000000;
msr.lo = 0x80fffe0;
wrmsr(MSR_GLIU0 + 0x21, msr);
msr.hi = 0x20000000;
msr.lo = 0xfff80;
wrmsr(MSR_GLIU1 + 0x20, msr);
msr.hi = 0x20000000;
msr.lo = 0x80fffe0;
wrmsr(MSR_GLIU1 + 0x21, msr);
}
static void mb_gpio_init(void)
{
/* Early mainboard specific GPIO setup. */
}
void cache_as_ram_main(void)
{
POST_CODE(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
};
SystemPreInit();
msr_init();
cs5536_early_setup();
/* Note: must do this AFTER the early_setup! It is counting on some
* early MSR setup for CS5536.
*/
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
mb_gpio_init();
uart_init();
console_init();
pll_reset(ManualConf);
cpuRegInit();
sdram_initialize(1, memctrl);
/* ram_check(0, 640 * 1024); */
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}

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src/mainboard/iei/pcisa-lx-800-r10/chip.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
extern struct chip_operations mainboard_iei_pcisa_lx_800_r10_ops;
struct mainboard_iei_pcisa_lx_800_r10_config {
int nothing;
};

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src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/pirq_routing.h>
// #include <console/console.h>
#include <arch/io.h>
/* Platform IRQs */
#define PIRQA 11
#define PIRQB 10
#define PIRQC 11
#define PIRQD 5
/* Link */
#define LINK_PIRQA 1
#define LINK_PIRQB 2
#define LINK_PIRQC 3
#define LINK_PIRQD 4
#define LINK_NONE 0
/* Map */
#define IRQ_BITMAP_LINKA (1 << PIRQA)
#define IRQ_BITMAP_LINKB (1 << PIRQB)
#define IRQ_BITMAP_LINKC (1 << PIRQC)
#define IRQ_BITMAP_LINKD (1 << PIRQD)
#define IRQ_BITMAP_NOLINK 0x0
#define EXCLUSIVE_PCI_IRQS (IRQ_BITMAP_LINKA | IRQ_BITMAP_LINKB | IRQ_BITMAP_LINKC | IRQ_BITMAP_LINKD)
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * IRQ_SLOT_COUNT,/* there can be total 6 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
EXCLUSIVE_PCI_IRQS, /* IRQs devoted exclusively to PCI usage */
0x1078, /* Vendor */
0x0002, /* Device */
0, /* Crap (miniport) */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
0x62, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
.slots = {
[0] = {
.slot = 0x0, /* means also "on board" */
.bus = 0x00,
.devfn = (0x01<<3)|0x0, /* 0x01 is CS5536 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQA,
.bitmap = IRQ_BITMAP_LINKA
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
}
}
},
[1] = {
.slot = 0x0, /* means also "on board" */
.bus = 0x00,
.devfn = (0x0f<<3)|0x0, /* 0x0f is CS5536 (USB, AUDIO) */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_PIRQB, /* Audio */
.bitmap = IRQ_BITMAP_LINKB
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_PIRQD, /* USB */
.bitmap = IRQ_BITMAP_LINKD
}
}
},
[2] = {
.slot = 0x0, /* means also "on board" */
.bus = 0x00,
.devfn = (0x0e<<3)|0x0, /* 0x0e is eth0 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQD,
.bitmap = IRQ_BITMAP_LINKD
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
}
}
},
[3] = {
.slot = 0x0, /* means also "on board" */
.bus = 0x00,
.devfn = (0x10<<3)|0x0, /* 0x10 is eth1 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQB,
.bitmap = IRQ_BITMAP_LINKB
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
}
}
},
[4] = {
.slot = 0x0, /* means also "on board" */
.bus = 0x00,
.devfn = (0x11<<3)|0x0, /* 0x11 is SATA */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQA,
.bitmap = IRQ_BITMAP_LINKA
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_NONE,
.bitmap = IRQ_BITMAP_NOLINK
}
}
},
/*
* ################### backplane ###################
*/
/*
* PCI1
*/
[5] = {
.slot = 0x1, /* This is real PCI slot. */
.bus = 0x00,
.devfn = (0x09<<3)|0x0, /* 0x09 is PCI1 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQA,
.bitmap = IRQ_BITMAP_LINKA
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_PIRQB,
.bitmap = IRQ_BITMAP_LINKB
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_PIRQC,
.bitmap = IRQ_BITMAP_LINKC
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_PIRQD,
.bitmap = IRQ_BITMAP_LINKD
}
}
},
/*
* PCI2
*/
[6] = {
.slot = 0x2, /* This is real PCI slot. */
.bus = 0x00,
.devfn = (0x0a<<3)|0x0, /* 0x0a is PCI2 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQD,
.bitmap = IRQ_BITMAP_LINKD
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_PIRQA,
.bitmap = IRQ_BITMAP_LINKA
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_PIRQB,
.bitmap = IRQ_BITMAP_LINKB
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_PIRQC,
.bitmap = IRQ_BITMAP_LINKC
}
}
},
/*
* PCI3
*/
[7] = {
.slot = 0x3, /* This is real PCI slot. */
.bus = 0x00,
.devfn = (0x0b<<3)|0x0, /* 0x0b is PCI3 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQC,
.bitmap = IRQ_BITMAP_LINKC
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_PIRQD,
.bitmap = IRQ_BITMAP_LINKD
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_PIRQA,
.bitmap = IRQ_BITMAP_LINKA
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_PIRQB,
.bitmap = IRQ_BITMAP_LINKB
}
}
},
/*
* PCI4
*/
[8] = {
.slot = 0x4, /* This is real PCI slot. */
.bus = 0x00,
.devfn = (0x0c<<3)|0x0, /* 0x0c is PCI4 */
.irq = {
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
.link = LINK_PIRQB,
.bitmap = IRQ_BITMAP_LINKB
},
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
.link = LINK_PIRQC,
.bitmap = IRQ_BITMAP_LINKC
},
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
.link = LINK_PIRQD,
.bitmap = IRQ_BITMAP_LINKD
},
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
.link = LINK_PIRQA,
.bitmap = IRQ_BITMAP_LINKA
}
}
},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
/* Put the PIR table in memory and checksum. */
return copy_pirq_routing_table(addr);
}

25
src/mainboard/iei/pcisa-lx-800-r10/mainboard.c Normal file
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@ -0,0 +1,25 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <device/device.h>
struct chip_operations mainboard_iei_pcisa_lx_800_r10_ops = {
CHIP_NAME("IEI PCISA-LX-800-R10 Mainboard")
};

46
targets/iei/pcisa-lx-800-r10/Config.lb Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
target pcisa-lx-800-r10
mainboard iei/pcisa-lx-800-r10
option CONFIG_COMPRESS = 0
option CONFIG_PRECOMPRESSED_PAYLOAD = 0
option CONFIG_COMPRESSED_PAYLOAD_NRV2B = 0
option CONFIG_COMPRESSED_PAYLOAD_LZMA = 0
# Leave 36k for VSA.
option ROM_SIZE = (512 * 1024) - (36 * 1024)
# option ROM_SIZE = (2048 * 1024) - (36 * 1024)
# Leave 36k for VSA, 1152k for bzImage and 750k for initrd.
# option ROM_SIZE = (2048 * 1024) - (36 * 1024) - (1152 * 1024) - (750 * 1024)
option FALLBACK_SIZE = ROM_SIZE
option DEFAULT_CONSOLE_LOGLEVEL = 0
option MAXIMUM_CONSOLE_LOGLEVEL = 0
romimage "fallback"
option USE_FALLBACK_IMAGE = 1
option ROM_IMAGE_SIZE = 80 * 1024
option COREBOOT_EXTRA_VERSION = ".0Fallback"
payload ../payload.elf
end
buildrom ./coreboot.rom ROM_SIZE "fallback"