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soc/intel/tigerlake: Enable end of post support in FSP 

Send end of post message to CSME in FSP, by selecting EndOfPost
message in PEI phase. In API mode which coreboot currently uses,
sending EndOfPost message in DXE phase is not applicable.

BUG=b:180755397
TEST=Extract and copy MEInfo tool from CSME Fit Kit to voxel, execute
  ./MEInfo | grep "BIOS Boot State"
and confirm response shows BIOS Boot State to be "Post Boot".

Change-Id: I1ad0d7cc06e79b2fe1e53d49c8e838f4d91af736
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51012
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nick Vaccaro 2021-02-22 14:26:13 -08:00
parent 3e945f1a23
commit 202b1899dc
1 changed files with 15 additions and 0 deletions
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15
src/soc/intel/tigerlake/fsp_params.c
View File

@ -34,6 +34,18 @@
#define DEF_DMVAL 15
#define DEF_DITOVAL 625
/*
* ME End of Post configuration
* 0 - Disable EOP.
* 1 - Send in PEI (Applicable for FSP in API mode)
* 2 - Send in DXE (Not applicable for FSP in API mode)
*/
enum {
EOP_DISABLE,
EOP_PEI,
EOP_DXE,
} EndOfPost;
/*
* Chip config parameter PcieRpL1Substates uses (UPD value + 1)
* because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
@ -203,6 +215,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->RtcMemoryLock = 1;
}
/* Enable End of Post in PEI phase */
params->EndOfPostMessage = EOP_PEI;
/* USB */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
params->PortUsb20Enable[i] = config->usb2_ports[i].enable;