vendorcode/amd/agesa/f*/cpcar.in: Remove non-GCC CAR implementation
We don't actually use nor support these as our implementation makes use of gcccar.inc. They maybe useful as a reference for history so lets keep them in version history. Change-Id: I388251dead449dde14283e57db39c37982d947b2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7596 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Edward O'Callaghan
parent
2697c0767b
commit
2031699011
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@ -1,477 +0,0 @@
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;*****************************************************************************
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; AMD Generic Encapsulated Software Architecture
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;
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; $Workfile:: cpcar.inc
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;
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; Description: CPCAR.INC - AGESA cache-as-RAM setup Include File
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;
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;*****************************************************************************
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;
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; Copyright (c) 2011, Advanced Micro Devices, Inc.
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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; * Neither the name of Advanced Micro Devices, Inc. nor the names of
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; its contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
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; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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;*****************************************************************************
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CORE0_STACK_BASE_ADDR EQU 40000h ;base address for primary cores stack
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CORE1_STACK_BASE_ADDR EQU 60000h ;base address for AP cores
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CORE0_STACK_SIZE EQU 4000h ;16KB for primary cores
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CORE1_STACK_SIZE EQU 1000h ;4KB for each AP cores
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AMD_MTRR_FIX64k_00000 EQU 250h
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AMD_MTRR_FIX16k_80000 EQU 258h
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AMD_MTRR_FIX16k_A0000 EQU 259h
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AMD_MTRR_FIX4k_C0000 EQU 268h
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AMD_MTRR_FIX4k_C8000 EQU 269h
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AMD_MTRR_FIX4k_D0000 EQU 26Ah
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AMD_MTRR_FIX4k_D8000 EQU 26Bh
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AMD_MTRR_FIX4k_E0000 EQU 26Ch
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AMD_MTRR_FIX4k_E8000 EQU 26Dh
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AMD_MTRR_FIX4k_F0000 EQU 26Eh
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AMD_MTRR_FIX4k_F8000 EQU 26Fh
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AMD_MTRR_DEFTYPE EQU 2FFh
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AMD_MTRR_VARIABLE_BASE6 EQU 020Ch
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TOP_MEM EQU 0C001001Ah
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MtrrFixDramEn EQU 18
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MtrrFixDramModEn EQU 19
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MtrrVarDramEn EQU 20
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WB_DRAM_TYPE EQU 1Eh
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HWCR EQU 0C0010015h
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INVD_WBINVD EQU 4
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LS_CFG EQU 0C0011020h
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DisStreamSt EQU 28
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IC_CFG EQU 0C0011021h
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DIS_SPEC_TLB_RLD EQU 9
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DIS_IND EQU 14
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BU_CFG2 EQU 0C001102Ah
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ClLinesToNbDis EQU 15
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DC_DIS_SPEC_TLB_RLD EQU 4 ; disable speculative TLB reloads
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DIS_CLR_WBTOL2_SMC_HIT EQU 8 ; self modifying code check buffer bit
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DIS_HW_PF EQU 13 ; hardware prefetches bit
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IC_DIS_SPEC_TLB_RLD EQU 9 ; disable speculative TLB reloads
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CR0_CD EQU 40000000h ; CR0[30] = Cache Disable
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CR0_NW EQU 20000000h ; CR0[29] = Not Writethrough
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; CPUID Functions
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CPUID_MODEL EQU 1
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AMD_CPUID_FMF EQU 80000001h ; Family Model Features information
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NB_CFG EQU 0C001001Fh
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bEnableCF8ExtCfg EQU 00004000h ; [46]
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bInitAPICCPUIDLo EQU 00400000h ; [54]
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MTRR_SYS_CFG EQU 0C0010010h
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ChxToDirtyDis EQU 16
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SysUcLockEn EQU 17
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MtrrFixDramEn EQU 18
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MtrrFixDramModEn EQU 19
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MtrrVarDramEn EQU 20
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MtrrTom2En EQU 21
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PERF_COUNTER3 EQU 0C0010007h ; Performance event counter three
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PERF_CONTROL3 EQU 0C0010003h ; Performance event control three
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PERF_CONTROL3_RESERVE_L EQU 00200000h ; Preserve the reserved bits
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PERF_CONTROL3_RESERVE_H EQU 0FCF0h ; Preserve the reserved bits
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CONFIG_EVENT_L EQU 0F0E2h ; All cores with level detection
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CONFIG_EVENT_H EQU 4 ; Increment count by number of event
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; occured in clock cycle
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EVENT_ENABLE EQU 22 ; Enable the event
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;;***************************************************************************
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;;
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;; CPU MACROS - PUBLIC
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;;
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;;***************************************************************************
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_WRMSR macro
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db 0Fh, 30h
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endm
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_RDMSR macro
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db 0Fh, 32h
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endm
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;----------------------------------------------
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;
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; AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless
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;
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;----------------------------------------------
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AMD_DISABLE_STACK_FAMILY_HOOK MACRO
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AMD_DISABLE_STACK_FAMILY_HOOK_F10
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AMD_DISABLE_STACK_FAMILY_HOOK_F14
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ENDM
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AMD_DISABLE_STACK_FAMILY_HOOK_F10 MACRO
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local cl_line_to_nb_enable_exit
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AMD_CPUID CPUID_MODEL
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shr eax, 20 ; AL = cpu extended family
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cmp al, 01h ; Is this family 10h?
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jnz cl_line_to_nb_enable_exit ; Br if no
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; For Family 10h, clear BU_CFG2[15] ClLinesToNbDis bit to Re-Enable L3 cache
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; Warning: icache for ROM (IO space) is disabled
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mov ecx, 0C001102Ah ; BU_CFG2
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_RDMSR
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btr eax, 15
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btr edx, 3
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_WRMSR
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; * MSRC001_1021[DIS_IND]=0. Disable indirect branch predictor.
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mov ecx, IC_CFG ; IC_CFG
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_RDMSR
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btr eax, DIS_IND ; turn off Disable indirect branch predictor
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_WRMSR
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;--------------------------------------------------------------------------
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; Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
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;--------------------------------------------------------------------------
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; Disable INVD_WBINVD across the invd instruction.
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mov cx, 0015h ; HWCR
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_RDMSR
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mov bx, ax ; save INVD -> WBINVD bit
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and al, 0EFh ; disable INVD -> WBINVD conversion
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_WRMSR
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invd ; Clear the cache tag RAMs
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; Restore INVD_WBINVD
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mov ax, bx ; restore INVD -> WBINVD bit
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_WRMSR
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;--------------------------------------------------------------------------
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; End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
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;--------------------------------------------------------------------------
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mov ecx, PERF_CONTROL3 ; Select the event control three
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_RDMSR ; Retrieve the current value
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btc eax, EVENT_ENABLE ; Is event enable, complement it as well
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jnc cl_line_to_nb_enable_exit ; No
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cmp ax, CONFIG_EVENT_L ; Is the lower part of event set to capture the CAR Corruption
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jne cl_line_to_nb_enable_exit ; No
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cmp dl, CONFIG_EVENT_H ; Is the upper part of event set to capture the CAR Corruption
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jne cl_line_to_nb_enable_exit ; No
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_WRMSR ; Disable the event
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cl_line_to_nb_enable_exit:
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ENDM
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AMD_DISABLE_STACK_FAMILY_HOOK_F14 MACRO
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local fam14_enable_stack_hook_exit
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;
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; For Family 14h
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;
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; Restore the following configuration state:
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; * MSRC001_0015[INVD_WBINVD]=1.
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; * MSRC001_1020[DisStreamSt]=0.
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; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0.
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; * MSRC001_1022[DIS_HW_PF]=0.
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;
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; When BIOS is done executing from WP-IO the following steps are followed:
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; * MSRC001_102A[ClLinesToNbDis]=1.
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AMD_CPUID CPUID_MODEL
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shr eax, 20 ; AL = cpu extended family
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cmp al, 05h ; Is this family 10h?
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jnz fam14_enable_stack_hook_exit ; Br if no
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; * MSRC001_0015[INVD_WBINVD]=0.
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mov ecx, HWCR
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_RDMSR
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bts eax, INVD_WBINVD ; turn off Convert INVD to WBINVD bit
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_WRMSR
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; * MSRC001_1020[DisStreamSt]=1.
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mov ecx, LS_CFG
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_RDMSR
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btr eax, DisStreamSt ; turn on Streaming store functionality disabled bit
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_WRMSR
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; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1. Disable speculative ITLB reloads.
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inc ecx ; mov ecx, IC_CFG
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_RDMSR
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btr eax, DIS_SPEC_TLB_RLD ; turn on Disable speculative TLB reloads bit
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_WRMSR
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; * MSRC001_1022[DIS_HW_PF]=1.
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inc ecx
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_RDMSR
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btr eax, DIS_HW_PF ; turn on Disable hardware prefetches bit
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_WRMSR
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fam14_enable_stack_hook_exit:
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ENDM
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;---------------------------------------------------
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;
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; AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless
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;
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;---------------------------------------------------
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AMD_ENABLE_STACK_FAMILY_HOOK MACRO
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AMD_ENABLE_STACK_FAMILY_HOOK_F10
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AMD_ENABLE_STACK_FAMILY_HOOK_F14
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ENDM
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AMD_ENABLE_STACK_FAMILY_HOOK_F10 MACRO
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local cl_line_to_nb_disable_exit
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AMD_CPUID CPUID_MODEL
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shr eax, 20 ; AL = cpu extended family
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cmp al, 01h ; Is this family 10h?
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jnz cl_line_to_nb_disable_exit ; Br if no
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; For Family 10h, set BU_CFG2[15] ClLinesToNbDis bit to disable L3 cache
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; Allow BIOS ROM to be cached in the IC
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mov ecx, 0C001102Ah ; BU_CFG2
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_RDMSR
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bts eax, 15
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bts edx, 3
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_WRMSR
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mov cx, 0015h ; HWCR
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_RDMSR
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and al, 0EFh ; disable INVD -> WBINVD conversion
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_WRMSR
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; * MSRC001_1021[DIS_IND]=1. Disable indirect branch predictor.
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mov ecx, IC_CFG ; IC_CFG
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_RDMSR
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bts eax, DIS_IND ; turn on Disable indirect branch predictor
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_WRMSR
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.if (di == 0) ;core 0
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mov ecx, PERF_COUNTER3 ; Select performance counter three
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; to count number of CAR Corruption
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xor eax, eax ; Initialize the lower part of the counter to zero
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xor edx, edx ; Initializa the upper part of the counter to zero
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_WRMSR ; Save it
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mov ecx, PERF_CONTROL3 ; Select the event control three
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_RDMSR ; Get the current setting
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and eax, PERF_CONTROL3_RESERVE_L ; Preserve the reserved bits
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or eax, CONFIG_EVENT_L ; Set the lower part of event register to
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; select CAR Corruption occurred by any cores
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and dx, PERF_CONTROL3_RESERVE_H ; Preserve the reserved bits
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or dx, CONFIG_EVENT_H ; Set the upper part of event register
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_WRMSR ; Save it
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bts eax, EVENT_ENABLE ; Enable it
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_WRMSR ; Save it
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.endif
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cl_line_to_nb_disable_exit:
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ENDM
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AMD_ENABLE_STACK_FAMILY_HOOK_F14 MACRO
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local fam14_enable_stack_hook_exit
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;
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; For Family 14h
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;
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; The following requirements must be satisfied prior to using the cache as general storage:
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; * Paging must be disabled.
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; * MSRC001_0015[INVD_WBINVD]=0.
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; * MSRC001_1020[DisStreamSt]=1.
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; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1. Disable speculative ITLB reloads.
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; * MSRC001_1022[DIS_HW_PF]=1.
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; * MSRC001_102A[ClLinesToNbDis]=1.
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AMD_CPUID CPUID_MODEL
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shr eax, 20 ; AL = cpu extended family
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cmp al, 05h ; Is this family 10h?
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jnz fam14_enable_stack_hook_exit ; Br if no
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; * MSRC001_0015[INVD_WBINVD]=0.
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mov ecx, HWCR
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_RDMSR
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btr eax, INVD_WBINVD ; turn off Convert INVD to WBINVD bit
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_WRMSR
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; * MSRC001_1020[DisStreamSt]=1.
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mov ecx, LS_CFG
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_RDMSR
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bts eax, DisStreamSt ; turn on Streaming store functionality disabled bit
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_WRMSR
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; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1. Disable speculative ITLB reloads.
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inc ecx ; mov ecx, IC_CFG
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_RDMSR
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bts eax, DIS_SPEC_TLB_RLD ; turn on Disable speculative TLB reloads bit
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_WRMSR
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; * MSRC001_1022[DIS_HW_PF]=1.
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inc ecx
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_RDMSR
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bts eax, DIS_HW_PF ; turn on Disable hardware prefetches bit
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_WRMSR
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; * MSRC001_102A[ClLinesToNbDis]=1.
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mov ecx, BU_CFG2
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_RDMSR
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bts eax, ClLinesToNbDis ; turn on DC and IC caches WT/WP-IO, but L2 does not.
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_WRMSR
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fam14_enable_stack_hook_exit:
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ENDM
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;---------------------------------------------------
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;
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; GET_NODE_ID_CORE_ID Macro - Stackless
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;
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; Macro returns:
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; SI= NODE ID
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; DI= CORE ID
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;---------------------------------------------------
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GET_NODE_ID_CORE_ID MACRO
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GET_NODE_ID_CORE_ID_F10
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GET_NODE_ID_CORE_ID_F12
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GET_NODE_ID_CORE_ID_F14
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ENDM
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GET_NODE_ID_CORE_ID_F10 MACRO
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local node_core_f10_exit
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cmp si, -1 ; Has node/core already been discovered?
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jnz node_core_f10_exit ; Br if yes
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AMD_CPUID CPUID_MODEL
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shr eax, 20 ; AL = cpu extended family
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cmp al, 01h ; Is this family 10h?
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jnz node_core_f10_exit ; Br if no
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mov ecx, 1Bh ; APIC Base MSR
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_RDMSR
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xor si, si ; Assume BSC
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xor di, di
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test ah, 1 ; Is this the BSC?
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jnz node_core_f10_exit ; Br if yes
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mov ecx, 0C0000408h ; Read the family 10h mailbox
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_RDMSR
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mov si, dx ; SI = raw mailbox contents
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shr ebx, 24 ; BL = Initial APIC ID
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mov di, bx ; DI = Initial APIC ID
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AMD_CPUID 80000008h
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shr ch, 4 ; CH = ApicIdSize
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inc cl ; CL = Number of enabled cores in the socket
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mov bx, cx
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mov ecx, NB_CFG
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_RDMSR ; EDX bit 54-32=26 is InitApicIdCpuIdLo bit
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mov cl, bh ; CL = APIC ID size
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mov al, 1 ; Convert APIC ID size to an AND mask
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shl al, cl ; AL = 2^APIC ID size
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dec al ; AL = mask for relative core number
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xor ah, ah ; AX = mask for relative core number
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bt edx, 54-32 ; InitApicId == 1?
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.if (!carry?) ; Br if yes
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mov ch, 8 ; Calculate core number shift count
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sub ch, cl ; CH = core shift count
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mov cl, ch
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shr di, cl ; Right justify core number
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.endif
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and di, ax ; DI = socket-relative core number
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mov cx, si ; CX = raw mailbox value
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shr cx, 10 ; CL[1:0] = ModuleType
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and cl, 3 ; Isolate ModuleType
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xor bh, bh ; BX = Number of enabled cores in the socket
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shr bx, cl ; BX = Number of enabled cores per node
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xor dx, dx ; Clear upper word for div
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mov ax, di ; AX = socket-relative core number
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div bx ; DX = node-relative core number
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mov di, dx ; DI = node-relative core number
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and si, 000Fh ; SI = node number
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node_core_f10_exit:
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ENDM
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GET_NODE_ID_CORE_ID_F12 MACRO
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|
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local node_core_f12_exit
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cmp si, -1 ; Has node/core already been discovered?
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jnz node_core_f12_exit ; Br if yes
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|
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AMD_CPUID CPUID_MODEL
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shr eax, 20 ; AL = cpu extended family
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cmp al, 03h ; Is this family 10h?
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jnz node_core_f12_exit ; Br if no
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xor si, si ; Node must be 0
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shr ebx, 24 ; CPUID_0000_0001_EBX[31:24]: initial local APIC physical ID
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mov di, bx ; DI = core number
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node_core_f12_exit:
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ENDM
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GET_NODE_ID_CORE_ID_F14 MACRO
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local node_core_f14_exit
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cmp si, -1 ; Has node/core already been discovered?
|
||||
jnz node_core_f14_exit ; Br if yes
|
||||
|
||||
AMD_CPUID CPUID_MODEL
|
||||
shr eax, 20 ; AL = cpu extended family
|
||||
cmp al, 05h ; Is this family 14h?
|
||||
jnz node_core_f14_exit ; Br if no
|
||||
|
||||
xor si, si ; Node must be 0
|
||||
mov ecx, 1Bh ; APIC Base MSR
|
||||
_RDMSR
|
||||
xor di, di ; Assume BSC
|
||||
test ah, 1 ; Is this the BSC?
|
||||
jnz node_core_f14_exit ; Br if yes
|
||||
inc di ; Set core to 1
|
||||
node_core_f14_exit:
|
||||
ENDM
|
||||
|
||||
|
||||
AMD_CPUID MACRO arg0
|
||||
IFB <arg0>
|
||||
mov eax, 1
|
||||
db 0Fh, 0A2h ; Execute instruction
|
||||
bswap eax
|
||||
xchg al, ah ; Ext model in al now
|
||||
rol eax, 8 ; Ext model in ah, model in al
|
||||
and ax, 0FFCFh ; Keep 23:16, 7:6, 3:0
|
||||
ELSE
|
||||
mov eax, arg0
|
||||
db 0Fh, 0A2h
|
||||
ENDIF
|
||||
ENDM
|
||||
|
||||
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Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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Reference in New Issue