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rockchip/rk3399: correct sdram inc file DENALI_CTL_217_DATA value 

for per cs training, there should be more cycles to switch delay line.
so increase W2W_DIFFCS_DLY_F0 value from 0x1 to 0x5.

BRANCH=none
BUG=chrome-os-partner:54144
TEST=run "stressapptest -M 1024 -s 1000" and pass

Change-Id: I11720b7c6f009789b88ca26fc5da88597ed1622e
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 9de93beae09174d50a31d2df655529f71628f77c
Original-Change-Id: Ide23fff04fd63fb0afc538b610b7685756f79f8d
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/352953
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://review.coreboot.org/15307
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Lin Huang 2016-06-16 10:39:10 +08:00 committed by Martin Roth
parent 321a6a94f9
commit 203fe7278a
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/gru/sdram_inf/gru-sdram-lpddr3-hynix-4GB.inc
View File

@ -276,7 +276,7 @@
0x04040001, /* DENALI_CTL_214_DATA */ 0x04040001, /* DENALI_CTL_214_DATA */
0x0c0c0c04, /* DENALI_CTL_215_DATA */ 0x0c0c0c04, /* DENALI_CTL_215_DATA */
0x02080808, /* DENALI_CTL_216_DATA */ 0x02080808, /* DENALI_CTL_216_DATA */
0x02010103, /* DENALI_CTL_217_DATA */ 0x02050103, /* DENALI_CTL_217_DATA */
0x02010103, /* DENALI_CTL_218_DATA */ 0x02010103, /* DENALI_CTL_218_DATA */
0x00010103, /* DENALI_CTL_219_DATA */ 0x00010103, /* DENALI_CTL_219_DATA */
0x00020202, /* DENALI_CTL_220_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */

2
src/mainboard/google/gru/sdram_inf/kevin-sdram-lpddr3-hynix-4GB.inc
View File

@ -275,7 +275,7 @@
0x04030001, /* DENALI_CTL_214_DATA */ 0x04030001, /* DENALI_CTL_214_DATA */
0x08080803, /* DENALI_CTL_215_DATA */ 0x08080803, /* DENALI_CTL_215_DATA */
0x02080808, /* DENALI_CTL_216_DATA */ 0x02080808, /* DENALI_CTL_216_DATA */
0x02010203, /* DENALI_CTL_217_DATA */ 0x02050203, /* DENALI_CTL_217_DATA */
0x02010303, /* DENALI_CTL_218_DATA */ 0x02010303, /* DENALI_CTL_218_DATA */
0x00010203, /* DENALI_CTL_219_DATA */ 0x00010203, /* DENALI_CTL_219_DATA */
0x00020202, /* DENALI_CTL_220_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */