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sb/intel/i82801jx: Use PCI bitwise ops 

Tested with BUILD_TIMELESS=1, Intel DG43GT does not change.

Change-Id: Ifd5b8cd7644811a56afae82468c8eb0a7b6b7ff9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42157
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-06-08 02:09:33 +02:00 committed by Felix Held
parent efd23d92ef
commit 2048cb4386
10 changed files with 43 additions and 114 deletions
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10
src/southbridge/intel/i82801jx/bootblock.c
View File

@ -6,15 +6,7 @@
static void enable_spi_prefetch(void)
{
u8 reg8;
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 0);
reg8 = pci_read_config8(dev, 0xdc);
reg8 &= ~(3 << 2);
reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
pci_write_config8(dev, 0xdc, reg8);
pci_update_config8(PCI_DEV(0, 0x1f, 0), 0xdc, ~(3 << 2), 2 << 2);
}
void bootblock_early_southbridge_init(void)

7
src/southbridge/intel/i82801jx/early_init.c
View File

@ -59,9 +59,8 @@ void i82801jx_setup_bars(void)
/* Set up GPIOBASE. */
pci_write_config32(d31f0, D31F0_GPIO_BASE, DEFAULT_GPIOBASE);
/* Enable GPIO. */
pci_write_config8(d31f0, D31F0_GPIO_CNTL,
pci_read_config8(d31f0, D31F0_GPIO_CNTL) | 0x10);
/* Enable GPIO. */
pci_or_config8(d31f0, D31F0_GPIO_CNTL, 0x10);
}
#define TCO_BASE 0x60
@ -96,6 +95,8 @@ void i82801jx_early_init(void)
and 0xe (required if ME is disabled but present), bit 31 locks it.
The other bits are 'must write'. */
u8 reg8 = pci_read_config8(d31f0, 0xac);
/* FIXME: It's a 8-bit variable!!! */
reg8 |= (1 << 31) | (1 << 30) | (1 << 20) | (3 << 8);
pci_write_config8(d31f0, 0xac, reg8);

35
src/southbridge/intel/i82801jx/hdaudio.c
View File

@ -212,49 +212,30 @@ static void azalia_init(struct device *dev)
u8 *base;
struct resource *res;
u32 codec_mask;
u8 reg8;
u32 reg32;
// ESD
reg32 = pci_read_config32(dev, 0x134);
reg32 &= 0xff00ffff;
reg32 |= (2 << 16);
pci_write_config32(dev, 0x134, reg32);
pci_update_config32(dev, 0x134, ~0x00ff0000, 2 << 16);
// Link1 description
reg32 = pci_read_config32(dev, 0x140);
reg32 &= 0xff00ffff;
reg32 |= (2 << 16);
pci_write_config32(dev, 0x140, reg32);
pci_update_config32(dev, 0x140, ~0x00ff0000, 2 << 16);
// Port VC0 Resource Control Register
reg32 = pci_read_config32(dev, 0x114);
reg32 &= 0xffffff00;
reg32 |= 1;
pci_write_config32(dev, 0x114, reg32);
pci_update_config32(dev, 0x114, ~0x000000ff, 1);
// VCi traffic class
reg8 = pci_read_config8(dev, 0x44);
reg8 |= (7 << 0); // TC7
pci_write_config8(dev, 0x44, reg8);
pci_or_config8(dev, 0x44, 7 << 0);
// VCi Resource Control
reg32 = pci_read_config32(dev, 0x120);
reg32 |= (1 << 31);
reg32 |= (1 << 24); // VCi ID
reg32 |= (0x80 << 0); // VCi map
pci_write_config32(dev, 0x120, reg32);
pci_or_config32(dev, 0x120, (1 << 31) | (1 << 24) | (0x80 << 0)); /* VCi ID and map */
/* Set Bus Master */
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
reg8 = pci_read_config8(dev, 0x4d); // Docking Status
reg8 &= ~(1 << 7); // Docking not supported
pci_write_config8(dev, 0x4d, reg8);
// Docking not supported
pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status
/* Lock some R/WO bits by writing their current value. */
reg32 = pci_read_config32(dev, 0x74);
pci_write_config32(dev, 0x74, reg32);
pci_update_config32(dev, 0x74, ~0, 0);
res = find_resource(dev, 0x10);
if (!res)

18
src/southbridge/intel/i82801jx/i82801jx.c
View File

@ -34,7 +34,6 @@ static void i82801jx_pcie_init(const config_t *const info)
{
struct device *pciePort[6];
int i, slot_number = 1; /* Reserve slot number 0 for nb's PEG. */
u32 reg32;
/* PCIe - BIOS must program... */
for (i = 0; i < 6; ++i) {
@ -43,26 +42,21 @@ static void i82801jx_pcie_init(const config_t *const info)
printk(BIOS_EMERG, "PCIe port 00:1c.%x", i);
die(" is not listed in devicetree.\n");
}
reg32 = pci_read_config32(pciePort[i], 0x300);
pci_write_config32(pciePort[i], 0x300, reg32 | (1 << 21));
pci_or_config32(pciePort[i], 0x300, 1 << 21);
pci_write_config8(pciePort[i], 0x324, 0x40);
}
if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0))) {
for (i = 0; i < 6; ++i) {
if (pciePort[i]->enabled) {
reg32 = pci_read_config32(pciePort[i], 0xe8);
reg32 |= 1;
pci_write_config32(pciePort[i], 0xe8, reg32);
pci_or_config32(pciePort[i], 0xe8, 1);
}
}
}
for (i = 5; (i >= 0) && !pciePort[i]->enabled; --i) {
/* Only for the top disabled ports. */
reg32 = pci_read_config32(pciePort[i], 0x300);
reg32 |= 0x3 << 16;
pci_write_config32(pciePort[i], 0x300, reg32);
pci_or_config32(pciePort[i], 0x300, 0x3 << 16);
}
/* Set slot implemented, slot number and slot power limits. */
@ -88,10 +82,8 @@ static void i82801jx_pcie_init(const config_t *const info)
}
/* Lock R/WO ASPM support bits. */
for (i = 0; i < 6; ++i) {
reg32 = pci_read_config32(pciePort[i], 0x4c);
pci_write_config32(pciePort[i], 0x4c, reg32);
}
for (i = 0; i < 6; ++i)
pci_update_config32(pciePort[i], 0x4c, ~0, 0);
}
static void i82801jx_ehci_init(void)

18
src/southbridge/intel/i82801jx/lpc.c
View File

@ -160,8 +160,7 @@ static void i82801jx_power_options(struct device *dev)
int nmi_option;
/* BIOS must program... */
reg32 = pci_read_config32(dev, 0xac);
pci_write_config32(dev, 0xac, reg32 | (1 << 30) | (3 << 8));
pci_or_config32(dev, 0xac, (1 << 30) | (3 << 8));
/* Which state do we want to goto after g3 (power restored)?
* 0 == S0 Full On
@ -281,18 +280,13 @@ static void i82801jx_power_options(struct device *dev)
static void i82801jx_configure_cstates(struct device *dev)
{
u8 reg8;
reg8 = pci_read_config8(dev, D31F0_CxSTATE_CNF);
reg8 |= (1 << 4) | (1 << 3) | (1 << 2); // Enable Popup & Popdown
pci_write_config8(dev, D31F0_CxSTATE_CNF, reg8);
// Enable Popup & Popdown
pci_or_config8(dev, D31F0_CxSTATE_CNF, (1 << 4) | (1 << 3) | (1 << 2));
// Set Deeper Sleep configuration to recommended values
reg8 = pci_read_config8(dev, D31F0_C4TIMING_CNT);
reg8 &= 0xf0;
reg8 |= (2 << 2); // Deeper Sleep to Stop CPU: 34-40us
reg8 |= (2 << 0); // Deeper Sleep to Sleep: 15us
pci_write_config8(dev, D31F0_C4TIMING_CNT, reg8);
// Deeper Sleep to Stop CPU: 34-40us
// Deeper Sleep to Sleep: 15us
pci_update_config8(dev, D31F0_C4TIMING_CNT, ~0x0f, (2 << 2) | (2 << 0));
/* We could enable slow-C4 exit here, if someone needs it? */
}

8
src/southbridge/intel/i82801jx/pci.c
View File

@ -9,18 +9,14 @@
static void pci_init(struct device *dev)
{
u16 reg16;
u8 reg8;
/* This device has no interrupt */
pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff);
/* Master Latency Count must be set to 0x04! */
reg8 = pci_read_config8(dev, D30F0_SMLT);
reg8 &= 0x07;
reg8 |= (0x04 << 3);
pci_write_config8(dev, D30F0_SMLT, reg8);
pci_update_config8(dev, D30F0_SMLT, 0x07, 0x04 << 3);
/* Clear errors in status registers */
/* Clear errors in status registers. FIXME: Do something? */
reg16 = pci_read_config16(dev, PCI_STATUS);
//reg16 |= 0xf900;
pci_write_config16(dev, PCI_STATUS, reg16);

45
src/southbridge/intel/i82801jx/pcie.c
View File

@ -12,8 +12,6 @@
static void pci_init(struct device *dev)
{
u16 reg16;
u32 reg32;
struct southbridge_intel_i82801jx_config *config = dev->chip_info;
printk(BIOS_DEBUG, "Initializing ICH10 PCIe root port.\n");
@ -25,56 +23,39 @@ static void pci_init(struct device *dev)
// This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10);
reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
reg16 &= ~PCI_BRIDGE_CTL_PARITY;
reg16 |= PCI_BRIDGE_CTL_NO_ISA;
pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY,
PCI_BRIDGE_CTL_NO_ISA);
/* Enable IO xAPIC on this PCIe port */
reg32 = pci_read_config32(dev, 0xd8);
reg32 |= (1 << 7);
pci_write_config32(dev, 0xd8, reg32);
pci_or_config32(dev, 0xd8, 1 << 7);
/* Enable Backbone Clock Gating */
reg32 = pci_read_config32(dev, 0xe1);
reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0);
pci_write_config32(dev, 0xe1, reg32);
pci_or_config32(dev, 0xe1, (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
/* Set VC0 transaction class */
reg32 = pci_read_config32(dev, 0x114);
reg32 &= 0xffffff00;
reg32 |= 1;
pci_write_config32(dev, 0x114, reg32);
pci_update_config32(dev, 0x114, ~0x000000ff, 1);
/* Mask completion timeouts */
reg32 = pci_read_config32(dev, 0x148);
reg32 |= (1 << 14);
pci_write_config32(dev, 0x148, reg32);
pci_or_config32(dev, 0x148, 1 << 14);
/* Lock R/WO Correctable Error Mask. */
pci_write_config32(dev, 0x154, pci_read_config32(dev, 0x154));
pci_update_config32(dev, 0x154, ~0, 0);
/* Clear errors in status registers */
reg16 = pci_read_config16(dev, 0x06);
pci_write_config16(dev, 0x06, reg16);
reg16 = pci_read_config16(dev, 0x1e);
pci_write_config16(dev, 0x1e, reg16);
pci_update_config16(dev, 0x06, ~0, 0);
pci_update_config16(dev, 0x1e, ~0, 0);
/* Get configured ASPM state */
const enum aspm_type apmc = pci_read_config32(dev, 0x50) & 3;
/* If both L0s and L1 enabled then set root port 0xE8[1]=1 */
if (apmc == PCIE_ASPM_BOTH) {
reg32 = pci_read_config32(dev, 0xe8);
reg32 |= (1 << 1);
pci_write_config32(dev, 0xe8, reg32);
}
if (apmc == PCIE_ASPM_BOTH)
pci_or_config32(dev, 0xe8, 1 << 1);
/* Enable expresscard hotplug events. */
if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
pci_write_config32(dev, 0xd8,
pci_read_config32(dev, 0xd8)
| (1 << 30));
pci_or_config32(dev, 0xd8, 1 << 30);
pci_write_config16(dev, 0x42, 0x142);
}
}

3
src/southbridge/intel/i82801jx/sata.c
View File

@ -199,8 +199,7 @@ static void sata_init(struct device *const dev)
if (is_mobile && config->sata_traffic_monitor) {
struct device *const lpc_dev = pcidev_on_root(0x1f, 0);
if (((pci_read_config8(lpc_dev, D31F0_CxSTATE_CNF)
>> 3) & 3) == 3) {
if (((pci_read_config8(lpc_dev, D31F0_CxSTATE_CNF) >> 3) & 3) == 3) {
u8 reg8 = pci_read_config8(dev, 0x9c);
reg8 &= ~(0x1f << 2);
reg8 |= 3 << 2;

6
src/southbridge/intel/i82801jx/smbus.c
View File

@ -11,12 +11,8 @@
static void pch_smbus_init(struct device *dev)
{
u16 reg16;
/* Enable clock gating */
reg16 = pci_read_config16(dev, 0x80);
reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14));
pci_write_config16(dev, 0x80, reg16);
pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)));
}
static int lsmbus_read_byte(struct device *dev, u8 address)

7
src/southbridge/intel/i82801jx/thermal.c
View File

@ -14,11 +14,9 @@ static void thermal_init(struct device *dev)
return;
u8 reg8;
u32 reg32;
pci_write_config32(dev, 0x10, (uintptr_t)DEFAULT_TBAR);
reg32 = pci_read_config32(dev, 0x04);
pci_write_config32(dev, 0x04, reg32 | (1 << 1));
pci_or_config32(dev, 0x04, 1 << 1);
write32(DEFAULT_TBAR + 0x04, 0); /* Clear thermal trip points. */
write32(DEFAULT_TBAR + 0x44, 0);
@ -31,8 +29,7 @@ static void thermal_init(struct device *dev)
reg8 = read8(DEFAULT_TBAR + 0x48);
write8(DEFAULT_TBAR + 0x48, reg8 | (1 << 7));
reg32 = pci_read_config32(dev, 0x04);
pci_write_config32(dev, 0x04, reg32 & ~(1 << 1));
pci_and_config32(dev, 0x04, ~(1 << 1));
pci_write_config32(dev, 0x10, 0);
}