soc/intel/apollolake: Update SPI memory mapping constraints
MMIO region of 256 KiB under 4 GiB is not decoded by SPI controller by hardware design. Current code incorrectly specifies size of that region to be 128 KiB. This change corrects the value to 256 KiB. Change-Id: Idcc67eb3565b800d835e75c0b765dd49d1656938 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14979 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
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@ -23,8 +23,8 @@
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#include <fmap.h>
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#include <soc/intel/common/nvm.h>
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/* The 128 KiB right below 4G are decoded by readonly SRAM, not boot media */
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#define IFD_BIOS_MAX_MAPPED (CONFIG_IFD_BIOS_END - 128 * KiB)
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/* The 256 KiB right below 4G are decoded by readonly SRAM, not boot media */
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#define IFD_BIOS_MAX_MAPPED (CONFIG_IFD_BIOS_END - 256 * KiB)
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#define IFD_MAPPED_SIZE (IFD_BIOS_MAX_MAPPED - CONFIG_IFD_BIOS_START)
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#define IFD_BIOS_SIZE (CONFIG_IFD_BIOS_END - CONFIG_IFD_BIOS_START)
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