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device: Allow configuring bus mastering for PCI bridges conditionally 

Change-Id: Ic7cacce28f473dda76ca203016dbb8e00149a990
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Felix Singer 2020-09-07 15:21:21 +02:00 committed by Patrick Georgi
parent 81f5bf3017
commit 205b53ee77
2 changed files with 13 additions and 1 deletions
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11
src/device/Kconfig
View File

@ -534,9 +534,20 @@ config PCI_ALLOW_BUS_MASTER
if PCI_ALLOW_BUS_MASTER if PCI_ALLOW_BUS_MASTER
config PCI_SET_BUS_MASTER_PCI_BRIDGES
bool "PCI bridges"
default y
help
Let coreboot configure bus mastering for PCI bridges. Enabling bus
mastering for a PCI bridge also allows it to forward requests from
downstream devices. Currently, payloads ignore this and only enable
bus mastering for the downstream device. Hence, this option is needed
for compatibility until payloads are fixed.
config PCI_ALLOW_BUS_MASTER_ANY_DEVICE config PCI_ALLOW_BUS_MASTER_ANY_DEVICE
bool "Any devices" bool "Any devices"
default y default y
select PCI_SET_BUS_MASTER_PCI_BRIDGES
help help
Allow coreboot to enable PCI bus mastering for any device. The actual Allow coreboot to enable PCI bus mastering for any device. The actual
selection of devices depends on the various PCI drivers in coreboot. selection of devices depends on the various PCI drivers in coreboot.

3
src/device/pci_device.c
View File

@ -542,7 +542,8 @@ static void pci_set_resource(struct device *dev, struct resource *resource)
dev->command |= PCI_COMMAND_MEMORY; dev->command |= PCI_COMMAND_MEMORY;
if (resource->flags & IORESOURCE_IO) if (resource->flags & IORESOURCE_IO)
dev->command |= PCI_COMMAND_IO; dev->command |= PCI_COMMAND_IO;
if (resource->flags & IORESOURCE_PCI_BRIDGE) if (resource->flags & IORESOURCE_PCI_BRIDGE &&
CONFIG(PCI_SET_BUS_MASTER_PCI_BRIDGES))
dev->command |= PCI_COMMAND_MASTER; dev->command |= PCI_COMMAND_MASTER;
} }