GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/system76/oryp5: Configure dGPU GPIOs in bootblock 

Configure the dGPU power and reset pins in bootblock instead of
ramstage. This fixes a conflict with our downstream driver, which
configures these pins to enable dGPU power in romstage. Behavior remains
unchanged without the driver as the dGPU is left powered off.

Change-Id: Ica5ad5adc20fc2629d913b76a5a781fbd59a569d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Tim Crawford 2022-07-12 13:16:56 -06:00 committed by Martin L Roth
parent 4060df41b2
commit 205e7f676d
2 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/system76/oryp5/gpio.c
View File

@ -164,8 +164,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
// GPP_F22 (DGPU_RST#_PCH) configured in bootblock
// GPP_F23 (DGPU_PWR_EN) configured in bootblock
/* ------- GPIO Group GPP_G ------- */
PAD_NC(GPP_G0, NONE),

2
src/mainboard/system76/oryp5/gpio_early.c
View File

@ -6,6 +6,8 @@
static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
};
void mainboard_configure_early_gpios(void)