mb/system76/oryp5: Configure dGPU GPIOs in bootblock
Configure the dGPU power and reset pins in bootblock instead of ramstage. This fixes a conflict with our downstream driver, which configures these pins to enable dGPU power in romstage. Behavior remains unchanged without the driver as the dGPU is left powered off. Change-Id: Ica5ad5adc20fc2629d913b76a5a781fbd59a569d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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@ -164,8 +164,8 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
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PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
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PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
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PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
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PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
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PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
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// GPP_F22 (DGPU_RST#_PCH) configured in bootblock
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PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
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// GPP_F23 (DGPU_PWR_EN) configured in bootblock
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/* ------- GPIO Group GPP_G ------- */
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/* ------- GPIO Group GPP_G ------- */
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PAD_NC(GPP_G0, NONE),
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PAD_NC(GPP_G0, NONE),
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@ -6,6 +6,8 @@
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static const struct pad_config early_gpio_table[] = {
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static const struct pad_config early_gpio_table[] = {
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
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PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
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PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
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};
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};
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void mainboard_configure_early_gpios(void)
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void mainboard_configure_early_gpios(void)
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